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/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt7622-pcie-mirror.yaml40 reg = <0 0x10000400 0 0x10>;
/openbmc/u-boot/board/renesas/rsk7203/
H A Dlowlevel_init.S91 mov #0, r2
99 mov #0, r0
108 CCR1_D: .long 0x0000090B
109 PCCRL4_A: .long 0xFFFE3910
110 PCCRL4_D0: .word 0x0000
112 PECRL4_A: .long 0xFFFE3A10
113 PECRL4_D0: .word 0x0000
115 PECRL3_A: .long 0xFFFE3A12
116 PECRL3_D: .word 0x0000
118 PEIORL_A: .long 0xFFFE3A06
[all …]
/openbmc/u-boot/board/renesas/rsk7264/
H A Dlowlevel_init.S97 mov #0, r2
105 mov #0, r0
114 CCR1_D: .long 0x0000090B
115 FRQCR_A: .long 0xFFFE0010
116 FRQCR_D: .word 0x1003
118 STBCR3_A: .long 0xFFFE0408
119 STBCR3_D: .long 0x00000002
120 STBCR4_A: .long 0xFFFE040C
121 STBCR4_D: .word 0x0000
123 STBCR5_A: .long 0xFFFE0410
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm6328.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
55 #address-cells = <0>;
71 reg = <0x10000004 0x4>;
77 reg = <0x10000010 0x4>;
83 reg = <0x10000020 0x10>,
84 <0x10000030 0x10>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
140 reg = <0 0x43000000 0 0x30000>;
150 thermal-sensors = <&thermal 0>;
216 reg = <0 0x10000000 0 0x1000>;
223 reg = <0 0x10001000 0 0x250>;
[all …]
/openbmc/linux/drivers/video/fbdev/matrox/
H A Dmatroxfb_misc.c131 unsigned int bestdiff = ~0; in matroxfb_PLL_calcclock()
132 unsigned int bestvco = 0; in matroxfb_PLL_calcclock()
159 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) { in matroxfb_PLL_calcclock()
201 hw->SEQ[0] = 0x00; in matroxfb_vgaHWinit()
202 hw->SEQ[1] = 0x01; /* or 0x09 */ in matroxfb_vgaHWinit()
203 hw->SEQ[2] = 0x0F; /* bitplanes */ in matroxfb_vgaHWinit()
204 hw->SEQ[3] = 0x00; in matroxfb_vgaHWinit()
205 hw->SEQ[4] = 0x0E; in matroxfb_vgaHWinit()
206 …/* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064… in matroxfb_vgaHWinit()
220 /* GCTL is ignored when not using 0xA0000 aperture */ in matroxfb_vgaHWinit()
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
/openbmc/qemu/disas/
H A Dhppa.c50 #define PA_PAGESIZE 0x1000
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
[all …]