Home
last modified time | relevance | path

Searched +full:0 +full:x10000080 (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dbrcm,bcm6318-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 50>;
83 reg = <0x18 0x10>, <0x54 0x18>;
H A Dbrcm,bcm6328-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 32>;
83 reg = <0x18 0x10>;
H A Dbrcm,bcm6362-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 48>;
83 reg = <0x18 0x10>, <0x38 0x4>;
H A Dbrcm,bcm6368-gpio-sysctl.yaml35 "^gpio@[0-9a-f]+$":
44 "^pinctrl@[0-9a-f]+$":
68 reg = <0x10000080 0x80>;
69 ranges = <0 0x10000080 0x80>;
71 gpio@0 {
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 38>;
83 reg = <0x18 0x4>, <0x38 0x4>;
/openbmc/u-boot/board/netgear/dgnd3700v2/
H A Ddgnd3700v2.c9 #define GPIO_BASE_6362 0x10000080
11 #define GPIO_MODE_6362_REG 0x18
18 void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE); in board_early_init_f()
25 return 0; in board_early_init_f()
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm63268.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6318.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
61 reg = <0x10000008 0x4>;
74 reg = <0x10000010 0x4>;
80 reg = <0x10000068 0xc>;
[all …]
H A Dbrcm,bcm6368.dtsi20 reg = <0x10000000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
62 reg = <0x18000000 0x2000000>;
78 reg = <0x10000008 0x4>;
84 offset = <0x0>;
85 mask = <0x1>;
[all …]
H A Dbrcm,bcm6362.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
76 reg = <0x10000008 0x4>;
82 offset = <0x0>;
83 mask = <0x1>;
[all …]