Home
last modified time | relevance | path

Searched +full:0 +full:x10 (Results 1 – 25 of 1091) sorted by relevance

12345678910>>...44

/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt6765.c14 * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
15 * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200,
16 * iocfg[6]:0x10002500, iocfg[7]:0x10002600.
22 _x_bits, 32, 0)
29 PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
45 PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
46 PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
[all …]
H A Dpinctrl-mt6779.c13 * gpio:0x10005000, iocfg_rm:0x11C20000, iocfg_br:0x11D10000,
14 * iocfg_lm:0x11E20000, iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000,
15 * iocfg_lt:0x11F20000, iocfg_tl:0x11F30000
21 32, 0)
28 PIN_FIELD_BASE(0, 7, 0, 0x0300, 0x10, 0, 4),
29 PIN_FIELD_BASE(8, 15, 0, 0x0310, 0x10, 0, 4),
30 PIN_FIELD_BASE(16, 23, 0, 0x0320, 0x10, 0, 4),
31 PIN_FIELD_BASE(24, 31, 0, 0x0330, 0x10, 0, 4),
32 PIN_FIELD_BASE(32, 39, 0, 0x0340, 0x10, 0, 4),
33 PIN_FIELD_BASE(40, 47, 0, 0x0350, 0x10, 0, 4),
[all …]
H A Dpinctrl-mt8188.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11c00000, iocfg[2]:0x11e10000,
14 * iocfg[3]:0x11e20000, iocfg[4]:0x11ea0000
20 32, 0)
27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4),
31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1),
35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1),
39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1),
43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1),
44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1),
45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1),
[all …]
H A Dpinctrl-mt8186.c13 * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200,
14 * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800,
15 * iocfg[6]:0x10002C00.
20 PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
26 PIN_FIELD(0, 184, 0x300, 0x10, 0, 4),
30 PIN_FIELD(0, 184, 0x0, 0x10, 0, 1),
34 PIN_FIELD(0, 184, 0x200, 0x10, 0, 1),
38 PIN_FIELD(0, 184, 0x100, 0x10, 0, 1),
42 PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1),
43 PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1),
[all …]
H A Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]
H A Dpinctrl-mt8195.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
15 * iocfg[6]:0x11f40000.
21 32, 0)
28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
[all …]
H A Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
H A Dpinctrl-mt6795.c11 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
12 _x_bits, 15, 0)
15 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 16, 0)
19 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
23 PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
27 PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
31 PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
35 PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
39 PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
[all …]
H A Dpinctrl-mt7986.c11 #define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
17 _x_bits, 32, 0)
23 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
24 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
76 PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
80 PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
84 PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
88 PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
92 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
93 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
[all …]
H A Dpinctrl-mt7981.c12 MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
16 _x_bits, 32, 0)
23 PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
27 PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
31 PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
35 PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
39 PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
40 PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
41 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
42 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
[all …]
H A Dpinctrl-mt7623.c13 #define PIN_BOND_REG0 0xb10
14 #define PIN_BOND_REG1 0xf20
15 #define PIN_BOND_REG2 0xef0
16 #define BOND_PCIE_CLR (0x77 << 3)
17 #define BOND_I2S_CLR 0x3
18 #define BOND_MSDC0E_CLR 0x1
21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
26 _x_bits, 16, 0)
29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
[all …]
/openbmc/linux/fs/unicode/
H A Dutf8data.c_shipped8 0,
9 0x10100,
10 0x20000,
11 0x20100,
12 0x30000,
13 0x30100,
14 0x30200,
15 0x40000,
16 0x40100,
17 0x50000,
[all …]
/openbmc/linux/include/linux/mlx5/
H A Dmlx5_ifc.h38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
[all …]
H A Dmlx5_ifc_fpga.h36 u8 max_num_qps[0x10];
37 u8 reserved_at_10[0x8];
38 u8 total_rcv_credits[0x8];
40 u8 reserved_at_20[0xe];
41 u8 qp_type[0x2];
42 u8 reserved_at_30[0x5];
43 u8 rae[0x1];
44 u8 rwe[0x1];
45 u8 rre[0x1];
46 u8 reserved_at_38[0x4];
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-revc-lt2.dtsi9 pinctrl-0 = <&pinctrl_backlight>;
11 pwms = <&pwm2 0 20000 0>;
12 brightness-levels = <0 255>;
20 #size-cells = <0>;
24 pinctrl-0 = <&pinctrl_ipu1>;
26 port@0 {
27 reg = <0>;
63 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58
69 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
70 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
[all …]
H A Dimx6dl-skov-revc-lt6.dts17 pinctrl-0 = <&pinctrl_backlight>;
19 pwms = <&pwm2 0 20000 0>;
20 brightness-levels = <0 255>;
29 pinctrl-0 = <&pinctrl_ipu1>;
31 #size-cells = <0>;
33 port@0 {
34 reg = <0>;
70 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58
76 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
77 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
[all …]
H A Dimx6qdl-phytec-mira-peb-av-02.dtsi10 #size-cells = <0>;
13 pinctrl-0 = <&pinctrl_disp0>;
17 port@0 {
18 reg = <0>;
37 pinctrl-0 = <&pinctrl_disp0_pwr>;
62 pinctrl-0 = <&pinctrl_edt_ft5x06>;
63 reg = <0x38>;
77 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
[all …]
H A Dimx6q-skov-revc-lt6.dts17 pinctrl-0 = <&pinctrl_backlight>;
19 pwms = <&pwm2 0 20000 0>;
20 brightness-levels = <0 255>;
28 #size-cells = <0>;
32 pinctrl-0 = <&pinctrl_ipu1>;
34 port@0 {
35 reg = <0>;
71 pinctrl-0 = <&pinctrl_i2c2>;
83 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58
90 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878
[all …]
/openbmc/linux/drivers/media/usb/gspca/
H A Dsonixj.c64 #define BRIDGE_SN9C102P 0
94 #define F_PDN_INV 0x01 /* inverse pin S_PWR_DN / sn_xxx tables */
95 #define F_ILLUM 0x02 /* presence of illuminator */
98 /* register 0x01 */
99 #define S_PWR_DN 0x01 /* sensor power down */
100 #define S_PDN_INV 0x02 /* inverse pin S_PWR_DN */
101 #define V_TX_EN 0x04 /* video transfer enable */
102 #define LED 0x08 /* output to pin LED */
103 #define SCL_SEL_OD 0x20 /* open-drain mode */
104 #define SYS_SEL_48M 0x40 /* system clock 0: 24MHz, 1: 48MHz */
[all …]
H A Dnw80x.c159 * - 3rd byte: data length (=0 for end of sequence)
162 #define I2C0 0xff
165 0x04, 0x05, 0x01, 0x61,
166 0x04, 0x04, 0x01, 0x01,
167 0x04, 0x06, 0x01, 0x04,
168 0x04, 0x04, 0x03, 0x00, 0x00, 0x00,
169 0x05, 0x05, 0x01, 0x00,
170 0, 0, 0
173 0x04, 0x06, 0x01, 0xc0,
174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f,
[all …]
/openbmc/linux/lib/fonts/
H A Dfont_6x8.c7 { 0, 0, FONTDATAMAX, 0 }, {
8 /* 0 0x00 '^@' */
9 0x00, /* 000000 */
10 0x00, /* 000000 */
11 0x00, /* 000000 */
12 0x00, /* 000000 */
13 0x00, /* 000000 */
14 0x00, /* 000000 */
15 0x00, /* 000000 */
16 0x00, /* 000000 */
[all …]
H A Dfont_6x10.c7 { 0, 0, FONTDATAMAX, 0 }, {
8 /* 0 0x00 '^@' */
9 0x00, /* 00000000 */
10 0x00, /* 00000000 */
11 0x00, /* 00000000 */
12 0x00, /* 00000000 */
13 0x00, /* 00000000 */
14 0x00, /* 00000000 */
15 0x00, /* 00000000 */
16 0x00, /* 00000000 */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h27 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
28 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
29 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
30 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
31 …_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
32 …_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
33 …_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
34 …_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
36 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
37 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
[all …]
/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7623.c11 #define PIN_BOND_REG0 0xb10
12 #define PIN_BOND_REG1 0xf20
13 #define PIN_BOND_REG2 0xef0
14 #define BOND_PCIE_CLR (0x77 << 3)
15 #define BOND_I2S_CLR 0x3
16 #define BOND_MSDC0E_CLR 0x1
31 PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
35 PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
36 PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
40 PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Dmlx5_ifc_dr.h8 MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f,
12 u8 entry_type[0x4];
13 u8 reserved_at_4[0x4];
14 u8 entry_sub_type[0x8];
15 u8 byte_mask[0x10];
17 u8 next_table_base_63_48[0x10];
18 u8 next_lu_type[0x8];
19 u8 next_table_base_39_32_size[0x8];
21 u8 next_table_base_31_5_size[0x1b];
22 u8 linear_hash_enable[0x1];
[all …]

12345678910>>...44