Searched +full:0 +full:x030f0000 (Results 1 – 4 of 4) sorted by relevance
11 #define SUNXI_SRAM_C_BASE 0x0002800012 #define SUNXI_SRAM_A2_BASE 0x0010000014 #define SUNXI_DE3_BASE 0x0100000015 #define SUNXI_SS_BASE 0x0190400016 #define SUNXI_EMCE_BASE 0x0190500018 #define SUNXI_SRAMC_BASE 0x0300000019 #define SUNXI_CCM_BASE 0x0300100020 #define SUNXI_DMA_BASE 0x0300200021 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */22 #define SUNXI_SIDC_BASE 0x03006000[all …]
54 reg = <0x030f0000 0x10000>;
22 #define SMC_CLC_PROPOSAL 0x0123 #define SMC_CLC_ACCEPT 0x0224 #define SMC_CLC_CONFIRM 0x0325 #define SMC_CLC_DECLINE 0x0427 #define SMC_TYPE_R 0 /* SMC-R only */33 #define SMC_CLC_DECL_MEM 0x01010000 /* insufficient memory resources */34 #define SMC_CLC_DECL_TIMEOUT_CL 0x02010000 /* timeout w4 QP confirm link */35 #define SMC_CLC_DECL_TIMEOUT_AL 0x02020000 /* timeout w4 QP add link */36 #define SMC_CLC_DECL_CNFERR 0x03000000 /* configuration error */37 #define SMC_CLC_DECL_PEERNOSMC 0x03010000 /* peer did not indicate SMC */[all …]
22 #size-cells = <0>;24 cpu0: cpu@0 {27 reg = <0>;72 #clock-cells = <0>;114 reg = <0x1000000 0x400000>;118 ranges = <0 0x1000000 0x400000>;120 display_clocks: clock@0 {122 reg = <0x0 0x10000>;133 compatible = "allwinner,sun50i-h6-de3-mixer-0";134 reg = <0x100000 0x100000>;[all …]