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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml44 pattern: "^[a-z]+-noc@[0-9a-f]+$"
92 reg = <0x02300000 0x1000>;
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dcoredump.c16 .start = 0xe003b400,
17 .len = 0x00003bff,
24 .start = 0x00800000,
25 .len = 0x0005ffff,
29 .start = 0x00900000,
30 .len = 0x00013fff,
34 .start = 0x02200000,
35 .len = 0x0004ffff,
39 .start = 0x02300000,
40 .len = 0x0004ffff,
[all …]
/openbmc/u-boot/include/configs/
H A Dsocfpga_common.h20 #define PHYS_SDRAM_1 0x0
25 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
26 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
28 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
29 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
75 * that the address here is incremented by 0x400 from the Base address
76 * selected in QSys, since the SPI registers are at offset +0x400.
77 * #define CONFIG_SYS_SPI_BASE 0xff240400
96 * L4 OSC1 Timer 0
102 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]