Searched +full:0 +full:x021b4000 (Results 1 – 14 of 14) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/ |
H A D | mmdc.yaml | 44 reg = <0x021b0000 0x4000>; 50 reg = <0x021b4000 0x4000>;
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/openbmc/u-boot/board/freescale/mx6qarm2/ |
H A D | imximage_mx6dl.cfg | 39 DATA 4 0x020E04bc 0x00003028 41 DATA 4 0x020E04c0 0x00003028 43 DATA 4 0x020E04c4 0x00003028 45 DATA 4 0x020E04c8 0x00003028 47 DATA 4 0x020E04cc 0x00003028 49 DATA 4 0x020E04d0 0x00003028 51 DATA 4 0x020E04d4 0x00003028 53 DATA 4 0x020E04d8 0x00003028 56 DATA 4 0x020E0470 0x00000038 58 DATA 4 0x020E0474 0x00000038 [all …]
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H A D | imximage.cfg | 34 DATA 4 0x020C4018 0x60324 36 DATA 4 0x020E05a8 0x00003038 37 DATA 4 0x020E05b0 0x00003038 38 DATA 4 0x020E0524 0x00003038 39 DATA 4 0x020E051c 0x00003038 41 DATA 4 0x020E0518 0x00003038 42 DATA 4 0x020E050c 0x00003038 43 DATA 4 0x020E05b8 0x00003038 44 DATA 4 0x020E05c0 0x00003038 46 DATA 4 0x020E05ac 0x00000038 [all …]
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/openbmc/qemu/include/hw/arm/ |
H A D | fsl-imx6ul.h | 97 FSL_IMX6UL_MMDC_ADDR = 0x80000000, 100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, 103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, 106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, 109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, 112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, 116 FSL_IMX6UL_UART6_ADDR = 0x021FC000, 118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000, 120 FSL_IMX6UL_UART5_ADDR = 0x021F4000, 121 FSL_IMX6UL_UART4_ADDR = 0x021F0000, [all …]
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H A D | fsl-imx6.h | 84 #define FSL_IMX6_MMDC_ADDR 0x10000000 85 #define FSL_IMX6_MMDC_SIZE 0xF0000000 86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000 87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000 88 #define FSL_IMX6_IPU_2_ADDR 0x02800000 89 #define FSL_IMX6_IPU_2_SIZE 0x400000 90 #define FSL_IMX6_IPU_1_ADDR 0x02400000 91 #define FSL_IMX6_IPU_1_SIZE 0x400000 92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000 93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
H A D | mx6-ddr.h | 124 #define MX6SL_IOM_DDR_BASE 0x020e0300 150 #define MX6SL_IOM_GRP_BASE 0x020e0500 167 #define MX6UL_IOM_DDR_BASE 0x020e0200 190 #define MX6UL_IOM_GRP_BASE 0x020e0400 205 #define MX6SX_IOM_DDR_BASE 0x020e0200 231 #define MX6SX_IOM_GRP_BASE 0x020e0500 251 #define MX6DQ_IOM_DDR_BASE 0x020e0500 286 #define MX6DQ_IOM_GRP_BASE 0x020e0700 309 #define MX6SDL_IOM_DDR_BASE 0x020e0400 342 #define MX6SDL_IOM_GRP_BASE 0x020e0700 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx6sll.dtsi | 44 #size-cells = <0>; 46 cpu0: cpu@0 { 49 reg = <0>; 85 reg = <0x00a01000 0x1000>, 86 <0x00a00100 0x100>; 92 #size-cells = <0>; 94 ckil: clock@0 { 96 reg = <0>; 97 #clock-cells = <0>; 105 #clock-cells = <0>; [all …]
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H A D | imx6sl.dtsi | 24 memory { device_type = "memory"; reg = <0 0>; }; 48 #size-cells = <0>; 50 cpu@0 { 53 reg = <0x0>; 83 reg = <0x00a01000 0x1000>, 84 <0x00a00100 0x100>; 90 #size-cells = <0>; 94 #clock-cells = <0>; 100 #clock-cells = <0>; 114 reg = <0x00900000 0x20000>; [all …]
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H A D | imx6qdl.dtsi | 56 #clock-cells = <0>; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 68 #clock-cells = <0>; 76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 84 #size-cells = <0>; 89 lvds-channel@0 { 91 #size-cells = <0>; 92 reg = <0>; 95 port@0 { [all …]
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H A D | imx6sx.dtsi | 56 #size-cells = <0>; 58 cpu0: cpu@0 { 61 reg = <0>; 94 reg = <0x00a01000 0x1000>, 95 <0x00a00100 0x100>; 101 #size-cells = <0>; 103 ckil: clock@0 { 105 reg = <0>; 106 #clock-cells = <0>; 114 #clock-cells = <0>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6sll.dtsi | 47 #size-cells = <0>; 49 cpu0: cpu@0 { 52 reg = <0>; 82 #clock-cells = <0>; 89 #clock-cells = <0>; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 103 #clock-cells = <0>; 104 clock-frequency = <0>; 117 reg = <0x00900000 0x20000>; [all …]
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H A D | imx6sl.dtsi | 51 #size-cells = <0>; 53 cpu0: cpu@0 { 56 reg = <0x0>; 86 #clock-cells = <0>; 92 #clock-cells = <0>; 100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 105 #phy-cells = <0>; 117 reg = <0x00900000 0x20000>; 118 ranges = <0 0x00900000 0x20000>; 128 reg = <0x00a01000 0x1000>, [all …]
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H A D | imx6qdl.dtsi | 59 #clock-cells = <0>; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 71 #clock-cells = <0>; 78 #size-cells = <0>; 83 lvds-channel@0 { 85 #size-cells = <0>; 86 reg = <0>; 89 port@0 { 90 reg = <0>; [all …]
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H A D | imx6sx.dtsi | 61 #size-cells = <0>; 63 cpu0: cpu@0 { 66 reg = <0>; 100 #clock-cells = <0>; 107 #clock-cells = <0>; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 121 #clock-cells = <0>; 122 clock-frequency = <0>; 128 #clock-cells = <0>; [all …]
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