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12

/openbmc/linux/Documentation/devicetree/bindings/hwlock/
H A Dqcom-hwspinlock.yaml52 reg = <0x01f40000 0x40000>;
/openbmc/linux/arch/powerpc/boot/dts/
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9462_2p1_initvals.h63 {0x00000008, 0x00000000},
64 {0x00000030, 0x000e0085},
65 {0x00000034, 0x00000005},
66 {0x00000040, 0x00000000},
67 {0x00000044, 0x00000000},
68 {0x00000048, 0x00000008},
69 {0x0000004c, 0x00000010},
70 {0x00000050, 0x00000000},
71 {0x00001040, 0x002ffc0f},
72 {0x00001044, 0x002ffc0f},
[all …]
H A Dar9001_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
28 {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200},
[all …]
H A Dar5008_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
28 {0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200},
[all …]
H A Dar9002_initvals.h19 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
20 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
21 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
22 {0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
23 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
24 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
25 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
26 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
27 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
28 {0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300},
[all …]
H A Dar955x_1p0_initvals.h33 {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
34 {0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x0a566f3a, 0x0a566f3a},
35 {0x000160ac, 0xa4647c00, 0xa4647c00, 0x24647c00, 0x24647c00},
36 {0x000160b0, 0x01885f52, 0x01885f52, 0x01885f52, 0x01885f52},
37 {0x00016104, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
38 {0x0001610c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
39 {0x00016140, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
40 {0x00016504, 0xb7a00000, 0xb7a00000, 0xb7a00001, 0xb7a00001},
41 {0x0001650c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
42 {0x00016540, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
[all …]
H A Dar9565_1p0_initvals.h31 {0x00000008, 0x00000000},
32 {0x00000030, 0x000a0085},
33 {0x00000034, 0x00000005},
34 {0x00000040, 0x00000000},
35 {0x00000044, 0x00000000},
36 {0x00000048, 0x00000008},
37 {0x0000004c, 0x00000010},
38 {0x00000050, 0x00000000},
39 {0x00001040, 0x002ffc0f},
40 {0x00001044, 0x002ffc0f},
[all …]
H A Dar9330_1p1_initvals.h27 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
28 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
29 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
30 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
31 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
32 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
33 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
34 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
35 {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
36 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
[all …]
H A Dar9462_2p0_initvals.h33 {0x00001030, 0x00000268, 0x000004d0},
34 {0x00001070, 0x0000018c, 0x00000318},
35 {0x000010b0, 0x00000fd0, 0x00001fa0},
36 {0x00008014, 0x044c044c, 0x08980898},
37 {0x0000801c, 0x148ec02b, 0x148ec057},
38 {0x00008318, 0x000044c0, 0x00008980},
39 {0x00009e00, 0x0372131c, 0x0372131c},
40 {0x0000a230, 0x0000400b, 0x00004016},
41 {0x0000a254, 0x00000898, 0x00001130},
46 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
[all …]
H A Dar953x_initvals.h39 {0x00000008, 0x00000000},
40 {0x00000030, 0x00020085},
41 {0x00000034, 0x00000005},
42 {0x00000040, 0x00000000},
43 {0x00000044, 0x00000000},
44 {0x00000048, 0x00000008},
45 {0x0000004c, 0x00000010},
46 {0x00000050, 0x00000000},
47 {0x00001040, 0x002ffc0f},
48 {0x00001044, 0x002ffc0f},
[all …]
H A Dar9485_initvals.h31 {0x00009e00, 0x037216a0},
32 {0x00009e04, 0x00182020},
33 {0x00009e18, 0x00000000},
34 {0x00009e20, 0x000003a8},
35 {0x00009e2c, 0x00004121},
36 {0x00009e44, 0x02282324},
37 {0x0000a000, 0x00060005},
38 {0x0000a004, 0x00810080},
39 {0x0000a008, 0x00830082},
40 {0x0000a00c, 0x00850084},
[all …]
H A Dar9340_initvals.h37 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
38 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
39 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
40 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
41 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
46 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
47 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
48 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
49 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
50 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
[all …]
H A Dar9580_1p0_initvals.h29 {0x00016000, 0x36db2db6},
30 {0x00016004, 0x6db6db40},
31 {0x00016008, 0x73f00000},
32 {0x0001600c, 0x00000000},
33 {0x00016040, 0x7f80fff8},
34 {0x0001604c, 0x76d005b5},
35 {0x00016050, 0x556cf031},
36 {0x00016054, 0x13449440},
37 {0x00016058, 0x0c51c92c},
38 {0x0001605c, 0x3db7fffc},
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0 0x0>;
62 reg = <0x0 0x100>;
80 reg = <0x0 0x200>;
98 reg = <0x0 0x300>;
116 reg = <0x0 0x400>;
134 reg = <0x0 0x500>;
[all …]
H A Dsdx75.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
H A Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-dlink-dir-685.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
61 #size-cells = <0>;
70 panel: display@0 {
72 reg = <0>;
130 gpio-fan,speed-map = <0 0>, <10000 1>;
178 #size-cells = <0>;
182 reg = <0x26>;
203 #address-cells = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
H A Dhubgm107.fuc5.h3 /* 0x0000: hub_mmio_list_head */
4 0x00000300,
5 /* 0x0004: hub_mmio_list_tail */
6 0x00000304,
7 /* 0x0008: gpc_count */
8 0x00000000,
9 /* 0x000c: rop_count */
10 0x00000000,
11 /* 0x0010: cmd_queue */
12 0x00000000,
[all …]
H A Dhubgk208.fuc5.h3 /* 0x0000: hub_mmio_list_head */
4 0x00000300,
5 /* 0x0004: hub_mmio_list_tail */
6 0x00000304,
7 /* 0x0008: gpc_count */
8 0x00000000,
9 /* 0x000c: rop_count */
10 0x00000000,
11 /* 0x0010: cmd_queue */
12 0x00000000,
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
[all …]
H A Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dinitvals.c32 * @ini_mode: 0 to write 1 to read (and clear)
39 AR5K_INI_WRITE = 0, /* Default */
57 { AR5K_NOQCU_TXDP0, 0 },
58 { AR5K_NOQCU_TXDP1, 0 },
59 { AR5K_RXDP, 0 },
60 { AR5K_CR, 0 },
61 { AR5K_ISR, 0, AR5K_INI_READ },
62 { AR5K_IMR, 0 },
64 { AR5K_BSR, 0, AR5K_INI_READ },
70 { AR5K_RPGTO, 0 },
[all …]

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