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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-display-backend.yaml84 port@0:
95 - port@0
175 reg = <0x01e60000 0x10000>;
185 #size-cells = <0>;
187 port@0 {
189 #size-cells = <0>;
190 reg = <0>;
192 endpoint@0 {
193 reg = <0>;
205 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi11 #size-cells = <0>;
13 cpu0: cpu@0 {
16 reg = <0>;
84 reg = <0x01c00000 0x1000>;
91 reg = <0x00018000 0x1c000>;
94 ranges = <0 0x00018000 0x1c000>;
96 ve_sram: sram-section@0 {
99 reg = <0x000000 0x1c000>;
106 reg = <0x01c0e000 0x1000>;
117 reg = <0x01c15000 0x1000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33.dtsi127 cpu@0 {
201 sound-dai = <&codec 0>;
208 reg = <0x01c0e000 0x1000>;
219 reg = <0x01c15000 0x1000>;
228 #sound-dai-cells = <0>;
230 reg = <0x01c22c00 0x200>;
243 reg = <0x01c22e00 0x400>;
252 reg = <0x01c25000 0x100>;
253 #thermal-sensor-cells = <0>;
254 #io-channel-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a33.dtsi127 cpu@0 {
181 reg = <0x40000000 0x80000000>;
193 "Left DAC", "AIF1 Slot 0 Left",
194 "Right DAC", "AIF1 Slot 0 Right";
209 reg = <0x01c0c000 0x1000>;
222 #size-cells = <0>;
224 tcon0_in: port@0 {
226 #size-cells = <0>;
227 reg = <0>;
229 tcon0_in_drc0: endpoint@0 {
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-r40.c41 [AW_R40_DEV_SRAM_A1] = 0x00000000,
42 [AW_R40_DEV_SRAM_A2] = 0x00004000,
43 [AW_R40_DEV_SRAM_A3] = 0x00008000,
44 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
45 [AW_R40_DEV_SRAMC] = 0x01c00000,
46 [AW_R40_DEV_EMAC] = 0x01c0b000,
47 [AW_R40_DEV_MMC0] = 0x01c0f000,
48 [AW_R40_DEV_MMC1] = 0x01c10000,
49 [AW_R40_DEV_MMC2] = 0x01c11000,
50 [AW_R40_DEV_MMC3] = 0x01c12000,
[all …]