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/openbmc/linux/arch/mips/alchemy/
H A Dboard-gpr.c42 alchemy_gpio_direction_output(4, 0); in gpr_reset()
43 alchemy_gpio_direction_output(5, 0); in gpr_reset()
48 alchemy_gpio_direction_output(1, 0); in gpr_reset()
81 [0] = {
91 .id = 0,
99 * 0x00000000-0x00200000 : "kernel"
100 * 0x00200000-0x00a00000 : "rootfs"
101 * 0x01d00000-0x01f00000 : "config"
102 * 0x01c00000-0x01d00000 : "yamon"
103 * 0x01d00000-0x01d40000 : "yamon env vars"
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-linksys-panamera.dts19 memory@0 {
21 reg = <0x00000000 0x08000000>,
22 <0x88000000 0x08000000>;
27 reg = <0x1c080000 0x100000>;
83 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
136 reg = <0x200>;
138 #size-cells = <0>;
140 switch@0 {
143 #size-cells = <0>;
146 reg = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-h3.dtsi71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0>;
125 reg = <0x01c00000 0x30>;
132 reg = <0x01d00000 0x80000>;
135 ranges = <0 0x01d00000 0x80000>;
137 ve_sram: sram-section@0 {
140 reg = <0x000000 0x80000>;
147 reg = <0x01c40000 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,msm8916-venus.yaml77 reg = <0x01d00000 0xff000>;
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-h3.dtsi72 #size-cells = <0>;
74 cpu0: cpu@0 {
77 reg = <0>;
155 reg = <0x01400000 0x20000>;
168 reg = <0x01c00000 0x1000>;
175 reg = <0x01d00000 0x80000>;
178 ranges = <0 0x01d00000 0x80000>;
180 ve_sram: sram-section@0 {
183 reg = <0x000000 0x80000>;
190 reg = <0x01c0e000 0x1000>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-a23-a33.dtsi91 #size-cells = <0>;
93 cpu0: cpu@0 {
96 reg = <0>;
112 #clock-cells = <0>;
120 #clock-cells = <0>;
136 reg = <0x01c00000 0x30>;
143 reg = <0x01d00000 0x80000>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
151 reg = <0x000000 0x80000>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all …]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dlite5200b.dts22 gpios = <&gpt2 0 1>;
25 gpios = <&gpt3 0 1>;
34 memory@0 {
35 reg = <0x00000000 0x10000000>; // 256MB
41 cell-index = <0>;
87 phy0: ethernet-phy@0 {
88 reg = <0>;
95 reg = <0x50>;
101 reg = <0x8000 0x4000>;
106 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dpcm032.dts23 memory@0 {
24 reg = <0x00000000 0x08000000>; // 128MB
30 cell-index = <0>;
61 phy0: ethernet-phy@0 {
62 reg = <0>;
69 reg = <0x51>;
73 reg = <0x52>;
80 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 &mpc5200_pic 1 1 3
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dhardware.h35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
38 #define DAVINCI_UART0_BASE (0x01c20000)
39 #define DAVINCI_UART1_BASE (0x01c20400)
40 #define DAVINCI_TIMER3_BASE (0x01c20800)
41 #define DAVINCI_I2C_BASE (0x01c21000)
42 #define DAVINCI_TIMER0_BASE (0x01c21400)
43 #define DAVINCI_TIMER1_BASE (0x01c21800)
44 #define DAVINCI_WDOG_BASE (0x01c21c00)
[all …]
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
124 #clock-cells = <0>;
131 #clock-cells = <0>;
153 #size-cells = <0>;
164 simple-audio-card,dai-link@0 {
175 sound-dai = <&codec 0>;
197 polling-delay-passive = <0>;
198 polling-delay = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-r40.c41 [AW_R40_DEV_SRAM_A1] = 0x00000000,
42 [AW_R40_DEV_SRAM_A2] = 0x00004000,
43 [AW_R40_DEV_SRAM_A3] = 0x00008000,
44 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
45 [AW_R40_DEV_SRAMC] = 0x01c00000,
46 [AW_R40_DEV_EMAC] = 0x01c0b000,
47 [AW_R40_DEV_MMC0] = 0x01c0f000,
48 [AW_R40_DEV_MMC1] = 0x01c10000,
49 [AW_R40_DEV_MMC2] = 0x01c11000,
50 [AW_R40_DEV_MMC3] = 0x01c12000,
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916.dtsi26 reg = <0 0x80000000 0 0>;
35 reg = <0x0 0x86000000 0x0 0x300000>;
41 reg = <0x0 0x86300000 0x0 0x100000>;
49 reg = <0x0 0x86400000 0x0 0x100000>;
54 reg = <0x0 0x86500000 0x0 0x180000>;
59 reg = <0x0 0x86680000 0x0 0x80000>;
65 reg = <0x0 0x86700000 0x0 0xe0000>;
72 reg = <0x0 0x867e0000 0x0 0x20000>;
77 reg = <0x0 0x86800000 0x0 0x2b00000>;
82 reg = <0x0 0x89300000 0x0 0x600000>;
[all …]