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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dallwinner,sun7i-a20-gmac.txt20 reg = <0x01c50000 0x10000>,
21 <0x01c20164 0x4>;
22 interrupts = <0 85 1>;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dallwinner,sun7i-a20-gmac.yaml58 reg = <0x01c50000 0x10000>;
59 interrupts = <0 85 1>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-r40.dtsi59 #clock-cells = <0>;
66 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu@0 {
80 reg = <0>;
112 reg = <0x01c00030 0x0c>;
113 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
119 reg = <0x01c0f000 0x1000>;
124 pinctrl-0 = <&mmc0_pins>;
129 #size-cells = <0>;
[all …]
H A Dsun7i-a20.dtsi65 framebuffer@0 {
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
161 reg = <0x40000000 0x80000000>;
184 #clock-cells = <0>;
190 osc32k: clk@0 {
191 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-r40.c41 [AW_R40_DEV_SRAM_A1] = 0x00000000,
42 [AW_R40_DEV_SRAM_A2] = 0x00004000,
43 [AW_R40_DEV_SRAM_A3] = 0x00008000,
44 [AW_R40_DEV_SRAM_A4] = 0x0000b400,
45 [AW_R40_DEV_SRAMC] = 0x01c00000,
46 [AW_R40_DEV_EMAC] = 0x01c0b000,
47 [AW_R40_DEV_MMC0] = 0x01c0f000,
48 [AW_R40_DEV_MMC1] = 0x01c10000,
49 [AW_R40_DEV_MMC2] = 0x01c11000,
50 [AW_R40_DEV_MMC3] = 0x01c12000,
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all …]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]