Searched +full:0 +full:x01c2bc00 (Results 1 – 8 of 8) sorted by relevance
65 reg = <0x01c2bc00 0x400>;74 reg = <0x01c2bc00 0x400>;
11 #define SUNXI_SRAM_A1_BASE 0x0000000014 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */20 #define SUNXI_DE2_BASE 0x0100000023 #define SUNXI_CPUCFG_BASE 0x0170000026 #define SUNXI_SRAMC_BASE 0x01c0000027 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
67 /* Registers address (physical base address 0x01C2BC00) */68 #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */69 #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */70 #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */71 #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */72 #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */73 #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */74 #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */75 #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */76 #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;195 reg = <0x01c00000 0x30>;200 sram_a: sram@0 {202 reg = <0x00000000 0xc000>;205 ranges = <0 0x00000000 0xc000>;209 reg = <0x8000 0x4000>;[all …]
65 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;161 reg = <0x40000000 0x80000000>;184 #clock-cells = <0>;190 osc32k: clk@0 {191 #clock-cells = <0>;207 #clock-cells = <0>;214 #clock-cells = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
64 #clock-cells = <0>;72 #clock-cells = <0>;82 #size-cells = <0>;84 cpu0: cpu@0 {87 reg = <0>;130 polling-delay-passive = <0>;131 polling-delay = <0>;132 thermal-sensors = <&ths 0>;143 hysteresis = <0>;161 polling-delay-passive = <0>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]