Searched +full:0 +full:x01c20e00 (Results 1 – 13 of 13) sorted by relevance
16 pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$"31 reg = <0x01c20e00 0xc>;
97 reg = <0x01c20e00 0xc>;108 reg = <0x0300a000 0x400>;
90 reg = <0x01c20e00 0xc>;
60 reg = <0x01c20e00 0xc>;67 #sound-dai-cells = <0>;69 reg = <0x01c21000 0x400>;80 #sound-dai-cells = <0>;82 reg = <0x01c22400 0x400>;
78 reg = <0x01c16000 0x1000>;83 clock-names = "ahb", "mod", "pll-0", "pll-1";92 #size-cells = <0>;94 hdmi_in: port@0 {95 reg = <0>;110 reg = <0x01c20e00 0xc>;124 pinctrl-0 = <&mmc1_pins>;
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
94 reg = <0x01c20e00 0xc>;
60 reg = <0x01c20e00 0xc>;67 #sound-dai-cells = <0>;69 reg = <0x01c21000 0x400>;80 #sound-dai-cells = <0>;82 reg = <0x01c22400 0x400>;101 i2s0_data_pins_a: i2s0-data@0 {106 i2s0_mclk_pins_a: i2s0-mclk@0 {116 spdif_tx_pins_a: spdif@0 {122 uart1_cts_rts_pins_a: uart1-cts-rts@0 {
82 reg = <0x01c16000 0x1000>;87 clock-names = "ahb", "mod", "pll-0", "pll-1";96 #size-cells = <0>;98 hdmi_in: port@0 {99 reg = <0>;108 #size-cells = <0>;116 reg = <0x01c20e00 0xc>;131 uart0_pins_a: uart0@0 {150 mmc1_pins_a: mmc1@0 {
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;195 reg = <0x01c00000 0x30>;200 sram_a: sram@0 {202 reg = <0x00000000 0xc000>;205 ranges = <0 0x00000000 0xc000>;209 reg = <0x8000 0x4000>;[all …]
65 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;161 reg = <0x40000000 0x80000000>;184 #clock-cells = <0>;190 osc32k: clk@0 {191 #clock-cells = <0>;207 #clock-cells = <0>;214 #clock-cells = <0>;[all …]
11 #define SUNXI_SRAM_A1_BASE 0x0000000014 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */20 #define SUNXI_DE2_BASE 0x0100000023 #define SUNXI_CPUCFG_BASE 0x0170000026 #define SUNXI_SRAMC_BASE 0x01c0000027 #define SUNXI_DRAMC_BASE 0x01c01000[all …]