Searched +full:0 +full:x01c20d00 (Results 1 – 6 of 6) sorted by relevance
39 reg = <0x01c20d00 0x20>;
32 #define AW_A10_SRAM_A_BASE 0x0000000033 #define AW_A10_DRAMC_BASE 0x01c0100034 #define AW_A10_MMC0_BASE 0x01c0f00035 #define AW_A10_CCM_BASE 0x01c2000036 #define AW_A10_PIC_REG_BASE 0x01c2040037 #define AW_A10_PIT_REG_BASE 0x01c20c0038 #define AW_A10_UART0_REG_BASE 0x01c2800039 #define AW_A10_SPI0_BASE 0x01c0500040 #define AW_A10_EMAC_BASE 0x01c0b00041 #define AW_A10_EHCI_BASE 0x01c14000[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;195 reg = <0x01c00000 0x30>;200 sram_a: sram@0 {202 reg = <0x00000000 0xc000>;205 ranges = <0 0x00000000 0xc000>;209 reg = <0x8000 0x4000>;[all …]
65 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;161 reg = <0x40000000 0x80000000>;184 #clock-cells = <0>;190 osc32k: clk@0 {191 #clock-cells = <0>;207 #clock-cells = <0>;214 #clock-cells = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]