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/openbmc/linux/Documentation/devicetree/bindings/arm/sunxi/
H A Dallwinner,sun4i-a10-mbus.yaml143 reg = <0x01c01000 0x1000>;
147 dma-ranges = <0x00000000 0x40000000 0x20000000>;
154 reg = <0x01c62000 0x1000>,
155 <0x01c63000 0x1000>;
164 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun4i.h11 #define SUNXI_SRAM_A1_BASE 0x00000000
14 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20 #define SUNXI_DE2_BASE 0x01000000
23 #define SUNXI_CPUCFG_BASE 0x01700000
26 #define SUNXI_SRAMC_BASE 0x01c00000
27 #define SUNXI_DRAMC_BASE 0x01c01000
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-a10.c32 #define AW_A10_SRAM_A_BASE 0x00000000
33 #define AW_A10_DRAMC_BASE 0x01c01000
34 #define AW_A10_MMC0_BASE 0x01c0f000
35 #define AW_A10_CCM_BASE 0x01c20000
36 #define AW_A10_PIC_REG_BASE 0x01c20400
37 #define AW_A10_PIT_REG_BASE 0x01c20c00
38 #define AW_A10_UART0_REG_BASE 0x01c28000
39 #define AW_A10_SPI0_BASE 0x01c05000
40 #define AW_A10_EMAC_BASE 0x01c0b000
41 #define AW_A10_EHCI_BASE 0x01c14000
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]