Searched +full:0 +full:x01180000 (Results 1 – 8 of 8) sorted by relevance
9 #define OCRAM_BASE_ADDR 0x1000000010 #define OCRAM_SIZE 0x0001000011 #define OCRAM_BASE_S_ADDR 0x1001000012 #define OCRAM_S_SIZE 0x0001000014 #define CONFIG_SYS_IMMR 0x0100000015 #define CONFIG_SYS_DCSRBAR 0x2000000017 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)18 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)20 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)21 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)[all …]
162 reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,163 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,164 <0 0x01300000 0 0x50000>;
12 #define LAN9115 0x0115000013 #define LAN9116 0x0116000014 #define LAN9117 0x0117000015 #define LAN9118 0x0118000016 #define LAN9215 0x115A000017 #define LAN9216 0x116A000018 #define LAN9217 0x117A000019 #define LAN9218 0x118A000020 #define LAN9210 0x9210000021 #define LAN9211 0x92110000[all …]
11 #define CONFIG_SYS_IMMR 0x0100000012 #define CONFIG_SYS_DCSRBAR 0x2000000013 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)[all …]
26 #define mmGRBM_CNTL_DEFAULT 0x0000001827 #define mmGRBM_SKEW_CNTL_DEFAULT 0x0000002028 #define mmGRBM_STATUS2_DEFAULT 0x0000000029 #define mmGRBM_PWR_CNTL_DEFAULT 0x0000000030 #define mmGRBM_STATUS_DEFAULT 0x0000000031 #define mmGRBM_STATUS_SE0_DEFAULT 0x0000000032 #define mmGRBM_STATUS_SE1_DEFAULT 0x0000000033 #define mmGRBM_SOFT_RESET_DEFAULT 0x0000000034 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x0000010035 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008[all …]
26 #define mmSDMA0_DEC_START_DEFAULT 0x0000000027 #define mmSDMA0_PG_CNTL_DEFAULT 0x0000000028 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x0000000029 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x0000000030 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x0000000031 #define mmSDMA0_POWER_CNTL_DEFAULT 0x4000005032 #define mmSDMA0_CLK_CTRL_DEFAULT 0x0000010033 #define mmSDMA0_CNTL_DEFAULT 0x000000c234 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af010735 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044[all …]
63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x2201000164 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x2201000165 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x2201100266 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x2201100378 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L[all …]
77 #clock-cells = <0>;84 #clock-cells = <0>;91 #size-cells = <0>;93 CPU0: cpu@0 {96 reg = <0x0 0x0>;97 clocks = <&cpufreq_hw 0>;101 qcom,freq-domain = <&cpufreq_hw 0>;125 reg = <0x0 0x100>;126 clocks = <&cpufreq_hw 0>;130 qcom,freq-domain = <&cpufreq_hw 0>;[all …]