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/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME57 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
58 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
59 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
60 0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
61 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
62 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
63 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
64 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
72 0x30000000 - 0x37ffffff : 128MB : NOR flash
73 0x3C000000 - 0x40000000 : 64MB : CPLD
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi12 reg = <0x0 0xfd5b8000 0x0 0x10000>;
17 reg = <0x0 0xfd5c0000 0x0 0x100>;
22 reg = <0x0 0xfddc8000 0x0 0x1000>;
23 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
33 #sound-dai-cells = <0>;
39 reg = <0x0 0xfddf4000 0x0 0x1000>;
40 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
50 #sound-dai-cells = <0>;
56 reg = <0x0 0xfddf8000 0x0 0x1000>;
57 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/openbmc/linux/arch/microblaze/include/asm/
H A Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
[all …]
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME59 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
60 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
61 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
62 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
63 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
64 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
65 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
73 0x30000000 - 0x37ffffff : 128MB : NOR flash
74 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
75 0x3C000000 - 0x40000000 : 64MB : FPGA etc
[all …]
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dyellow_carp_offset.h19 static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
20 { { 0, 0, 0, 0, 0, 0 } },
21 { { 0, 0, 0, 0, 0, 0 } },
22 { { 0, 0, 0, 0, 0, 0 } },
23 { { 0, 0, 0, 0, 0, 0 } },
24 { { 0, 0, 0, 0, 0, 0 } },
25 { { 0, 0, 0, 0, 0, 0 } } } };
26 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
27 { { 0, 0, 0, 0, 0, 0 } },
28 { { 0, 0, 0, 0, 0, 0 } },
[all …]
H A Dnavi14_ip_offset.h39 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
47 { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
48 { { 0x00017000, 0x02402000, 0, 0, 0 } },
[all …]
H A Dsienna_cichlid_ip_offset.h39 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
47 { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
48 { { 0x00017000, 0x02402000, 0, 0, 0 } },
[all …]
H A Dbeige_goby_ip_offset.h40 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0, 0 } } } };
47 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
48 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
49 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
[all …]
H A Dvangogh_ip_offset.h42 static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0, 0 } },
49 { { 0, 0, 0, 0, 0, 0 } } } };
50 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
51 { { 0, 0, 0, 0, 0, 0 } },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dintel,keembay-pcie.yaml79 reg = <0x37000000 0x00001000>,
80 <0x37300000 0x00001000>,
81 <0x36e00000 0x00200000>,
82 <0x37800000 0x00000200>;
87 ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
/openbmc/u-boot/include/
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
/openbmc/linux/sound/soc/mxs/
H A Dmxs-saif.h10 #define SAIF_CTRL 0x0
11 #define SAIF_STAT 0x10
12 #define SAIF_DATA 0x20
13 #define SAIF_VERSION 0X30
16 #define BM_SAIF_CTRL_SFTRST 0x80000000
17 #define BM_SAIF_CTRL_CLKGATE 0x40000000
19 #define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
22 #define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
23 #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
24 #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-crs305-1g-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-crs328-4c-20s-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-crs326-24g-2s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl8712_xmit.h19 #define VO_QUEUE_INX 0
47 /*OFFSET 0*/
48 #define OFFSET_SZ (0)
54 #define TYPE_MSK (0x03000000)
57 #define PKT_OFFSET_SZ (0)
75 #define RSVD6_MSK (0x00E00000)
79 /*DWORD 0*/
/openbmc/qemu/target/microblaze/
H A Dcpu.h42 #define MB_CPU_IRQ 0
47 #define SR_PC 0
52 #define SR_BTR 0xb
53 #define SR_EDR 0xd
56 #define MSR_BE (1<<0) /* 0x001 */
57 #define MSR_IE (1<<1) /* 0x002 */
58 #define MSR_C (1<<2) /* 0x004 */
59 #define MSR_BIP (1<<3) /* 0x008 */
60 #define MSR_FSL (1<<4) /* 0x010 */
61 #define MSR_ICE (1<<5) /* 0x020 */
[all …]
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME12 RDB Default Switch Settings (1: ON; 0: OFF)
38 => i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21
68 QDS Default Switch Settings (1: ON; 0: OFF)
138 RCW+PBI 0x00000000
139 Boot firmware (U-Boot) 0x00100000
140 Boot firmware Environment 0x00300000
141 PPA firmware 0x00400000
142 DPAA2 MC 0x00A00000
143 DPAA2 DPL 0x00D00000
144 DPAA2 DPC 0x00E00000
[all …]
/openbmc/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2-xmc.dts47 bootargs = "earlycon=uart8250,mmio32,0x66130000";
52 reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
71 reg = <0x10>;
77 nandcs@0 {
79 reg = <0>;
88 partition@0 {
90 reg = <0x00000000 0x00280000>; /* 2.5MB */
96 reg = <0x00280000 0x00040000>; /* 0.25MB */
102 reg = <0x002c0000 0x00040000>; /* 0.25MB */
108 reg = <0x00300000 0x03d00000>; /* 61MB */
[all …]
/openbmc/u-boot/board/renesas/sh7763rdp/
H A Dlowlevel_init.S27 * 0xFFCC0008
37 write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
168 CCR_A: .long 0xFF00001C
169 MMUCR_A: .long 0xFF000010
170 RAMCR_A: .long 0xFF000074
173 MSTPCR0_A: .long 0xFFC80030
174 MSTPCR1_A: .long 0xFFC80038
177 WDTST_A: .long 0xFFCC0000
178 WDTCSR_A: .long 0xFFCC0004
179 WDTBST_A: .long 0xFFCC0008
[all …]
/openbmc/linux/drivers/crypto/bcm/
H A Dspum.h13 #define SPU_CRYPTO_OPERATION_GENERIC 0x1
19 #define SPU_STATUS_MASK 0x0000FF00
20 #define SPU_STATUS_SUCCESS 0x00000000
21 #define SPU_STATUS_INVALID_ICV 0x00000100
23 #define SPU_STATUS_ERROR_FLAG 0x00020000
72 __be16 offset_mac; /* word 0 [31-16] */
73 __be16 length_mac; /* word 0 [15-0] */
75 __be16 length_crypto; /* word 1 [15-0] */
77 __be16 offset_iv; /* word 2 [15-0] */
90 u16 reserved; /* [15:0] */
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h16 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
17 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
18 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
19 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
20 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
21 #define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
22 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
23 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
24 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
25 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.h9 #define BGMAC_DEV_CTL 0x000
10 #define BGMAC_DC_TSM 0x00000002
11 #define BGMAC_DC_CFCO 0x00000004
12 #define BGMAC_DC_RLSS 0x00000008
13 #define BGMAC_DC_MROR 0x00000010
14 #define BGMAC_DC_FCM_MASK 0x00000060
16 #define BGMAC_DC_NAE 0x00000080
17 #define BGMAC_DC_TF 0x00000100
18 #define BGMAC_DC_RDS_MASK 0x00030000
20 #define BGMAC_DC_TDS_MASK 0x000c0000
[all …]

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