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/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dmpc83xx.h8 #define MPC83XX_SCCR_OFFS 0xA08
9 #define MPC83XX_SCCR_USB_MASK 0x00f00000
10 #define MPC83XX_SCCR_USB_MPHCM_11 0x00c00000
11 #define MPC83XX_SCCR_USB_MPHCM_01 0x00400000
12 #define MPC83XX_SCCR_USB_MPHCM_10 0x00800000
13 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000
14 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000
15 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000
16 #define MPC8315_SCCR_USB_MASK 0x00c00000
17 #define MPC8315_SCCR_USB_DRCM_11 0x00c00000
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h135 #define CLKMGR_CTRL_SAFEMODE BIT(0)
136 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
146 #define CLKMGR_BYPASS_MAINPLL BIT(0)
147 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0
156 #define CLKMGR_STAT_BUSY BIT(0)
159 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0)
160 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
162 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
166 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
167 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood-atl-sbx81lifkw.dts14 reg = <0x00000000 0x08000000>; /* 128 MB */
31 #size-cells = <0>;
36 switch@0 {
38 #size-cells = <0>;
39 reg = <1 0>;
41 port@0 {
42 reg = <0>;
78 flash@0 {
82 reg = <0>;
84 mode = <0>;
[all …]
H A Dkirkwood-atl-sbx81lifxcat.dts14 reg = <0x00000000 0x08000000>; /* 128 MB */
31 #size-cells = <0>;
36 switch@0 {
38 #size-cells = <0>;
39 reg = <1 0>;
41 port@0 {
42 reg = <0>;
92 flash@0 {
96 reg = <0>;
98 mode = <0>;
[all …]
H A Dat91-sama5d2_xplained.dts15 gpios = <&pioA PIN_PB0 0>;
17 pinctrl-0 = <&pinctrl_onewire_tm_default>;
20 w1_eeprom: w1_eeprom@0 {
29 atmel,vbus-gpio = <&pioA 42 0>;
31 pinctrl-0 = <&pinctrl_usb_default>;
42 pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
50 pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
60 pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
84 flash@0 {
86 reg = <0>;
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-i2c.c18 #define CX18_REG_I2C_1_WR 0xf15000
19 #define CX18_REG_I2C_1_RD 0xf15008
20 #define CX18_REG_I2C_2_WR 0xf25100
21 #define CX18_REG_I2C_2_RD 0xf25108
23 #define SETSCL_BIT 0x0001
24 #define SETSDL_BIT 0x0002
25 #define GETSCL_BIT 0x0004
26 #define GETSDL_BIT 0x0008
28 #define CX18_CS5345_I2C_ADDR 0x4c
29 #define CX18_Z8F0811_IR_TX_I2C_ADDR 0x70
[all …]
/openbmc/linux/drivers/usb/gadget/udc/
H A Dfsl_qe_udc.h18 #define PORT_CPM 0
24 #define USB_MAX_CTRL_PAYLOAD 0x4000
31 #define USB_DIR_BOTH 0x88
32 #define R_BUF_MAXSIZE 0x800
36 #define USB_MODE_EN 0x01
37 #define USB_MODE_HOST 0x02
38 #define USB_MODE_TEST 0x04
39 #define USB_MODE_SFTE 0x08
40 #define USB_MODE_RESUME 0x40
41 #define USB_MODE_LSS 0x80
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5272.h20 #define GPIO_PACNT_PA15MSK (0xC0000000)
21 #define GPIO_PACNT_DGNT1 (0x40000000)
22 #define GPIO_PACNT_PA14MSK (0x30000000)
23 #define GPIO_PACNT_DREQ1 (0x10000000)
24 #define GPIO_PACNT_PA13MSK (0x0C000000)
25 #define GPIO_PACNT_DFSC3 (0x04000000)
26 #define GPIO_PACNT_PA12MSK (0x03000000)
27 #define GPIO_PACNT_DFSC2 (0x01000000)
28 #define GPIO_PACNT_PA11MSK (0x00C00000)
29 #define GPIO_PACNT_QSPI_CS1 (0x00800000)
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dbluestone.dts16 dcr-parent = <&{/cpus/cpu@0}>;
26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 cell-index = <0>;
53 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
[all …]
H A Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
H A Damigaone.dts20 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
29 timebase-frequency = <0>; // 33.3 MHz, from U-boot
30 clock-frequency = <0>; // From U-boot
31 bus-frequency = <0>; // From U-boot
37 reg = <0 0>; // From U-boot
44 bus-range = <0 0xff>;
45 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
46 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ssbi.yaml50 reg = <0x00c00000 0x1000>;
60 #size-cells = <0>;
/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dmal.h37 #define MAL_CFG 0x00
38 #define MAL_CFG_SR 0x80000000
39 #define MAL_CFG_PLBB 0x00004000
40 #define MAL_CFG_OPBBL 0x00000080
41 #define MAL_CFG_EOPIE 0x00000004
42 #define MAL_CFG_LEA 0x00000002
43 #define MAL_CFG_SD 0x00000001
46 #define MAL1_CFG_PLBP_MASK 0x00c00000
47 #define MAL1_CFG_PLBP_10 0x00800000
48 #define MAL1_CFG_GA 0x00200000
[all …]
H A Demac.h103 #define EMAC_MR0_RXI 0x80000000
104 #define EMAC_MR0_TXI 0x40000000
105 #define EMAC_MR0_SRST 0x20000000
106 #define EMAC_MR0_TXE 0x10000000
107 #define EMAC_MR0_RXE 0x08000000
108 #define EMAC_MR0_WKE 0x04000000
111 #define EMAC_MR1_FDE 0x80000000
112 #define EMAC_MR1_ILE 0x40000000
113 #define EMAC_MR1_VLE 0x20000000
114 #define EMAC_MR1_EIFC 0x10000000
[all …]
/openbmc/linux/drivers/dma/
H A Dfsldma.h19 #define FSL_DMA_MR_CS 0x00000001
20 #define FSL_DMA_MR_CC 0x00000002
21 #define FSL_DMA_MR_CA 0x00000008
22 #define FSL_DMA_MR_EIE 0x00000040
23 #define FSL_DMA_MR_XFE 0x00000020
24 #define FSL_DMA_MR_EOLNIE 0x00000100
25 #define FSL_DMA_MR_EOLSIE 0x00000080
26 #define FSL_DMA_MR_EOSIE 0x00000200
27 #define FSL_DMA_MR_CDSM 0x00000010
28 #define FSL_DMA_MR_CTM 0x00000004
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1-apf9328.dts19 reg = <0x08000000 0x00800000>;
25 pinctrl-0 = <&pinctrl_i2c>;
31 pinctrl-0 = <&pinctrl_uart1>;
38 pinctrl-0 = <&pinctrl_uart2>;
45 pinctrl-0 = <&pinctrl_weim>;
48 nor: flash@0,0 {
50 reg = <0 0x00000000 0x02000000>;
52 fsl,weim-cs-timing = <0x00330e04 0x00000d01>;
59 pinctrl-0 = <&pinctrl_eth>;
61 reg = <4 0x00c00000 0x2>,
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h18 #define BR0 0x5000 /* Register offset to immr */
19 #define BR1 0x5008
20 #define BR2 0x5010
21 #define BR3 0x5018
22 #define BR4 0x5020
23 #define BR5 0x5028
24 #define BR6 0x5030
25 #define BR7 0x5038
27 #define BR_BA 0xFFFF8000
29 #define BR_XBA 0x00006000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_packets.h14 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull
17 PACKET_WREG_32 = 0x1,
18 PACKET_WREG_BULK = 0x2,
19 PACKET_MSG_LONG = 0x3,
20 PACKET_MSG_SHORT = 0x4,
21 PACKET_CP_DMA = 0x5,
22 PACKET_REPEAT = 0x6,
23 PACKET_MSG_PROT = 0x7,
24 PACKET_FENCE = 0x8,
25 PACKET_LIN_DMA = 0x9,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,msm8996-venus.yaml112 reg = <0x00c00000 0xff000>;
120 iommus = <&venus_smmu 0x00>,
121 <&venus_smmu 0x01>,
122 <&venus_smmu 0x0a>,
123 <&venus_smmu 0x07>,
124 <&venus_smmu 0x0e>,
125 <&venus_smmu 0x0f>,
126 <&venus_smmu 0x08>,
127 <&venus_smmu 0x09>,
128 <&venus_smmu 0x0b>,
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dsm712.h23 #define dac_reg (0x3c8)
24 #define dac_val (0x3c9)
31 #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
32 #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
33 #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
34 #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
35 #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
36 #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
37 #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
38 #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
[all …]
/openbmc/u-boot/board/renesas/lager/
H A Dlager_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/include/configs/
H A DUCP1020.h27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
120 #define CONFIG_SYS_CCSRBAR 0xffe00000
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
[all …]
/openbmc/linux/arch/powerpc/platforms/embedded6xx/
H A Dmpc10x.h24 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
25 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
26 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
29 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
30 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
31 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
40 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
41 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
42 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
49 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
[all …]

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