Searched +full:0 +full:x0021b000 (Results 1 – 5 of 5) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | imx1-clock.yaml | 41 reg = <0x0021b000 0x1000>;
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/openbmc/linux/drivers/clk/imx/ |
H A D | clk-imx1.c | 17 #define MX1_CCM_BASE_ADDR 0x0021b000 18 #define MX1_TIM1_BASE_ADDR 0x00220000 29 #define CCM_CSCR (ccm + 0x0000) 30 #define CCM_MPCTL0 (ccm + 0x0004) 31 #define CCM_SPCTL0 (ccm + 0x000c) 32 #define CCM_PCDR (ccm + 0x0020) 33 #define SCM_GCCR (ccm + 0x0810) 37 ccm = of_iomap(np, 0); in mx1_clocks_init_dt() 40 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx1_clocks_init_dt() 47 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in mx1_clocks_init_dt() [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx1.dtsi | 38 reg = <0x00223000 0x1000>; 42 #size-cells = <0>; 45 cpu@0 { 47 reg = <0>; 59 #clock-cells = <0>; 75 reg = <0x00200000 0x10000>; 80 reg = <0x00202000 0x1000>; 89 reg = <0x00203000 0x1000>; 98 reg = <0x00205000 0x1000>; 109 reg = <0x00206000 0x1000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap5-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */ 13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */ 14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */ 15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */ 16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */ [all …]
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H A D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x4a000000 */ 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ [all …]
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