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Searched +full:0 +full:x0010f000 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dnvidia,tegra186-misc.yaml41 reg = <0x00100000 0xf000>,
42 <0x0010f000 0x1000>;
/openbmc/qemu/include/hw/xen/interface/
H A Dtrace.h17 #define TRC_GEN 0x0001f000 /* General trace */
18 #define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */
19 #define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */
20 #define TRC_HVM 0x0008f000 /* Xen HVM trace */
21 #define TRC_MEM 0x0010f000 /* Xen memory trace */
22 #define TRC_PV 0x0020f000 /* Xen PV traces */
23 #define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */
24 #define TRC_HW 0x0080f000 /* Xen hardware-related traces */
25 #define TRC_GUEST 0x0800f000 /* Guest-generated traces */
26 #define TRC_ALL 0x0ffff000
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
[all …]
H A Drk3588s.dtsi23 #size-cells = <0>;
58 cpu_l0: cpu@0 {
61 reg = <0x0>;
82 reg = <0x100>;
101 reg = <0x200>;
120 reg = <0x300>;
139 reg = <0x400>;
160 reg = <0x500>;
179 reg = <0x600>;
200 reg = <0x700>;
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode-arm.c19 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
21 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
72 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2); in simulate_blx1()
79 int rm = insn & 0xf; in simulate_blx2bx()
85 regs->ARM_pc = rmv & ~0x1; in simulate_blx2bx()
87 if (rmv & 0x1) in simulate_blx2bx()
94 int rd = (insn >> 12) & 0xf; in simulate_mrs()
95 unsigned long mask = 0xf8ff03df; /* Mask out execution state */ in simulate_mrs()
122 DECODE_SIMULATE (0xfe300000, 0xf4100000, PROBES_PRELOAD_IMM),
128 DECODE_SIMULATE (0xfe300010, 0xf6100000, PROBES_PRELOAD_REG),
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
[all …]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]