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/openbmc/linux/arch/arm/mach-ep93xx/
H A Dep93xx-regs.h14 #define EP93XX_AHB_PHYS_BASE 0x80000000
15 #define EP93XX_AHB_VIRT_BASE 0xfef00000
16 #define EP93XX_AHB_SIZE 0x00100000
21 #define EP93XX_APB_PHYS_BASE 0x80800000
22 #define EP93XX_APB_VIRT_BASE 0xfed00000
23 #define EP93XX_APB_SIZE 0x00200000
29 #define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000)
30 #define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
32 #define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000)
33 #define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
[all …]
/openbmc/linux/drivers/media/platform/qcom/venus/
H A Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmpc8349_pci.h5 #define M8265_PCIBR0 0x101ac
6 #define M8265_PCIBR1 0x101b0
7 #define M8265_PCIMSK0 0x101c4
8 #define M8265_PCIMSK1 0x101c8
12 #define PCIBR_ENABLE 0x00000001
16 #define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
17 #define PCIMSK_64KB 0xFFFF0000
18 #define PCIMSK_128KB 0xFFFE0000
19 #define PCIMSK_256KB 0xFFFC0000
20 #define PCIMSK_512KB 0xFFF80000
[all …]
/openbmc/u-boot/arch/x86/cpu/tangier/
H A Dsdram.c17 * physical address 0x000E0000 and 0x000FFFFF. U-Boot shall search this region
21 #define SFI_BASE_ADDR 0x000E0000
22 #define SFI_LENGTH 0x00020000
27 char chksum = 0; in sfi_table_check()
37 for (i = 0; i < sbh->len; i++) in sfi_table_check()
44 return chksum ? -EILSEQ : 0; in sfi_table_check()
59 for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) { in sfi_get_table_by_sig()
85 for (i = 0; i < sys_entry_cnt; i++) { in sfi_search_mmap()
97 for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry; \
107 int type, total = 0; in sfi_setup_e820()
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/openbmc/linux/arch/powerpc/boot/
H A Ddcr.h8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
25 #define DCRN_SDRAM0_CFGADDR 0x010
26 #define DCRN_SDRAM0_CFGDATA 0x011
35 #define SDRAM0_B0CR 0x40
36 #define SDRAM0_B1CR 0x44
37 #define SDRAM0_B2CR 0x48
38 #define SDRAM0_B3CR 0x4c
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-test/fwts/fwts/
H A D0005-Undefine-PAGE_SIZE.patch19 #define BIOS_START (0x000e0000) /* Start of BIOS memory */
20 #define BIOS_END (0x000fffff) /* End of BIOS memory */
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-lenovo-ix4-300d.dts23 memory@0 {
25 reg = <0 0x00000000 0 0x20000000>; /* 512MB */
29 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
30 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
40 pinctrl-0 = <&ge0_rgmii_pins>;
48 pinctrl-0 = <&ge1_rgmii_pins>;
69 reg = <0x2e>;
74 reg = <0x50>;
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/openbmc/u-boot/include/configs/
H A Dsocfpga_sr1500.h11 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
14 #define CONFIG_LOADADDR 0x01000000
36 #define CONFIG_ENV_OFFSET 0x000e0000
H A Dwb50n.h40 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
43 #define CONFIG_SYS_INIT_SP_ADDR 0x310000
49 #define CONFIG_SYS_MEMTEST_START 0x21000000
50 #define CONFIG_SYS_MEMTEST_END 0x22000000
70 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
73 "autoload=no\0" \
74 "autostart=no\0"
77 #define CONFIG_ENV_OFFSET 0xA0000
78 #define CONFIG_ENV_OFFSET_REDUND 0xC0000
79 #define CONFIG_ENV_SIZE 0x20000
[all …]
/openbmc/linux/include/linux/mfd/
H A Dezx-pcap.h40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
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/openbmc/linux/drivers/video/fbdev/geode/
H A Dvideo_cs5530.h18 #define CS5530_VIDEO_CONFIG 0x0000
19 # define CS5530_VCFG_VID_EN 0x00000001
20 # define CS5530_VCFG_VID_REG_UPDATE 0x00000002
21 # define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
22 # define CS5530_VCFG_8_BIT_4_2_0 0x00000004
23 # define CS5530_VCFG_16_BIT_4_2_0 0x00000008
24 # define CS5530_VCFG_GV_SEL 0x00000010
25 # define CS5530_VCFG_CSC_BYPASS 0x00000020
26 # define CS5530_VCFG_X_FILTER_EN 0x00000040
27 # define CS5530_VCFG_Y_FILTER_EN 0x00000080
[all …]
H A Ddisplay_gx1.h21 #define CONFIG_CCR3 0xc3
22 # define CONFIG_CCR3_MAPEN 0x10
23 #define CONFIG_GCR 0xb8
27 #define MC_BANK_CFG 0x08
28 # define MC_BCFG_DIMM0_SZ_MASK 0x00000700
29 # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
30 # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
32 #define MC_GBASE_ADD 0x14
33 # define MC_GADD_GBADD_MASK 0x000003ff
37 #define DC_PAL_ADDRESS 0x70
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Dnettel.c30 #define AMD_WINDOW_MAXSIZE 0x00200000
36 #define SC520_PAR_ADDR_MASK 0x00003fff
41 #define SC520_PAR_SIZE_MASK 0x01ffc000
51 #define SC520_PAR_BOOTCS 0x8a000000
52 #define SC520_PAR_ROMCS1 0xaa000000
53 #define SC520_PAR_ROMCS2 0xca000000 /* Cache disabled, 64K page */
69 .size = 0,
76 .offset = 0,
77 .size = 0x000e0000
81 .offset = 0x00100000,
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnvidia,tegra186-timer.yaml45 One per each timer channels 0 through 9.
57 One per each timer channels 0 through 15.
73 reg = <0x03010000 0x000e0000>;
74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 reg = <0x02080000 0x00121000>;
93 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
/openbmc/linux/Documentation/arch/arm/sa1100/
H A Dassabet.rst91 load zImage -r -b 0x100000
95 load -m ymodem -r -b 0x100000
99 fis create "Linux kernel" -b 0x100000 -l 0xc0000
108 load ramdisk_image.gz -r -b 0x800000
119 exec -b 0x100000 -l 0xc0000
140 load sample_img.jffs2 -r -b 0x100000
144 RedBoot> load sample_img.jffs2 -r -b 0x100000
145 Raw file loaded 0x00100000-0x00377424
154 0x500E0000 .. 0x503C0000
162 size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
[all …]
/openbmc/u-boot/arch/x86/include/asm/fsp/
H A Dfsp_fv.h11 #define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
12 #define EFI_FV_FILE_ATTR_FIXED 0x00000100
13 #define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
16 #define EFI_FVB2_READ_DISABLED_CAP 0x00000001
17 #define EFI_FVB2_READ_ENABLED_CAP 0x00000002
18 #define EFI_FVB2_READ_STATUS 0x00000004
19 #define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
20 #define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
21 #define EFI_FVB2_WRITE_STATUS 0x00000020
22 #define EFI_FVB2_LOCK_CAP 0x00000040
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
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/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dstart.S21 move.w #0x2700,%sr; /* disable intrs */ \
47 INITSP: .long 0 /* Initial SP */
57 INITSP: .long 0 /* Initial SP */
75 /* TRAP #0 - #15 */
119 .long 0x00000000 /* checksum, not yet implemented */
120 .long 0x00040000 /* image length */
124 move.w #0x2700,%sr /* Mask off Interrupt */
143 move.l #0, %d0
152 move.l #0, %d0
163 move.l #0xFC008000, %a1
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4018-jalapeno.dts72 pinctrl-0 = <&spi_0_pins>;
76 flash@0 {
80 reg = <0>;
88 partition@0 {
90 reg = <0x00000000 0x00040000>;
96 reg = <0x00040000 0x00020000>;
102 reg = <0x00060000 0x00060000>;
108 reg = <0x000c0000 0x00010000>;
114 reg = <0x000d0000 0x00010000>;
120 reg = <0x000e0000 0x00010000>;
[all …]
H A Dqcom-ipq4018-ap120c-ac.dtsi102 pinctrl-0 = <&i2c0_pins>;
107 reg = <0x29>;
114 pinctrl-0 = <&spi0_pins>;
118 flash@0 {
120 reg = <0>;
128 partition@0 {
130 reg = <0x00000000 0x00040000>;
136 reg = <0x00040000 0x00020000>;
142 reg = <0x00060000 0x00060000>;
148 reg = <0x000c0000 0x00010000>;
[all …]
/openbmc/qemu/pc-bios/optionrom/
H A Dpvh_main.c30 #define RSDP_SIGNATURE 0x2052545020445352LL /* "RSD PTR " */
31 #define RSDP_AREA_ADDR 0x000E0000
32 #define RSDP_AREA_SIZE 0x00020000
33 #define EBDA_BASE_ADDR 0x0000040E
39 /* e820 table filled in pvh.S using int 0x15 */
66 return 0; in search_rsdp()
83 * because we can use int 0x15 only in real mode. in pvh_load_kernel()
102 if (ebda_paddr > 0x400) { in pvh_load_kernel()
/openbmc/linux/drivers/scsi/bfa/
H A Dbfi_reg.h18 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
19 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
20 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
21 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
22 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
23 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
24 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
25 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
27 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
28 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/openbmc/linux/drivers/net/ethernet/brocade/bna/
H A Dbfi_reg.h19 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
20 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
21 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
22 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
23 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
24 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
25 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
26 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
28 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
29 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts14 cpu@0 {
21 reg = <0x80000000 0x10000000>; /* 256 MB */
29 gpios = <&gpio1 5 0>;
37 pinctrl-0 = <&misc_pins>;
162 pinctrl-0 = <&uart0_pins>;
168 pinctrl-0 = <&uart1_pins>;
179 pinctrl-0 = <&uart2_pins>;
189 pinctrl-0 = <&uart3_pins>;
200 pinctrl-0 = <&uart4_pins>;
211 pinctrl-0 = <&uart5_pins>;
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dsouthcluster.asl11 Name(_ADR, 0)
12 Name(_BBN, 0)
18 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
20 /* IO Region 0 */
22 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
25 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
29 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
31 /* VGA memory (0xa0000-0xbffff) */
34 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
35 0x00020000, , , ASEG)
[all …]

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