| /openbmc/u-boot/drivers/video/ |
| H A D | logicore_dp_dpcd.h | 16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
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| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
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| /openbmc/linux/arch/mips/include/asm/sgi/ |
| H A D | hpc3.h | 22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
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| /openbmc/linux/arch/powerpc/include/asm/book3s/64/ |
| H A D | mmu-hash.h | 34 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
41 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
42 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
43 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
44 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
45 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
47 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
48 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
49 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
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| /openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/ |
| H A D | rtl8xxxu_8192f.c | 34 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
35 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
36 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
37 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
38 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
39 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
40 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
41 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
42 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
43 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
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| /openbmc/linux/drivers/perf/hisilicon/ |
| H A D | hns3_pmu.c | 29 #define HNS3_PMU_REG_GLOBAL_CTRL 0x0000
30 #define HNS3_PMU_REG_CLOCK_FREQ 0x0020
31 #define HNS3_PMU_REG_BDF 0x0fe0
32 #define HNS3_PMU_REG_VERSION 0x0fe4
33 #define HNS3_PMU_REG_DEVICE_ID 0x0fe8
35 #define HNS3_PMU_REG_EVENT_OFFSET 0x1000
36 #define HNS3_PMU_REG_EVENT_SIZE 0x1000
37 #define HNS3_PMU_REG_EVENT_CTRL_LOW 0x00
38 #define HNS3_PMU_REG_EVENT_CTRL_HIGH 0x04
39 #define HNS3_PMU_REG_EVENT_INTR_STATUS 0x08
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| /openbmc/linux/drivers/phy/ |
| H A D | phy-xgene.c | 28 * indirectly from the SDS offset at 0x2000. It is only required for
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
31 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
36 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
53 #define SERDES_PLL_INDIRECT_OFFSET 0x0000
54 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
55 #define SERDES_INDIRECT_OFFSET 0x0400
56 #define SERDES_LANE_STRIDE 0x0200
59 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
60 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
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| /openbmc/linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.c | 44 gpu->name, __builtin_return_address(0), in a6xx_idle()
119 OUT_RING(ring, 0); in a6xx_set_pagetable()
132 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); in a6xx_set_pagetable()
133 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); in a6xx_set_pagetable()
161 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); in a6xx_set_pagetable()
162 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); in a6xx_set_pagetable()
163 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); in a6xx_set_pagetable()
164 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); in a6xx_set_pagetable()
178 unsigned int i, ibs = 0; in a6xx_submit()
182 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), in a6xx_submit()
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| /openbmc/linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | rtw8723d.c | 19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 },
20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 },
21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 },
22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 },
23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff },
24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 },
25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 },
26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 },
27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff },
28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 },
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