| /openbmc/linux/arch/x86/um/ |
| H A D | delay.c | 15 "test %0,%0\n" in __delay()
23 "2: dec %0\n" in __delay()
25 "3: dec %0\n" in __delay()
40 : "1" (xloops), "0" in __const_udelay()
49 __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */ in __udelay()
55 __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */ in __ndelay()
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| /openbmc/u-boot/drivers/video/ |
| H A D | logicore_dp_dpcd.h | 16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
[all …]
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| /openbmc/linux/arch/x86/lib/ |
| H A D | delay.c | 45 " test %0,%0 \n" in delay_loop()
53 "2: dec %0 \n" in delay_loop()
55 "3: dec %0 \n" in delay_loop()
134 __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0); in delay_halt_mwaitx()
137 * AMD, like Intel, supports the EAX hint and EAX=0xf means, do not in delay_halt_mwaitx()
154 * Timer value of 0 causes MWAITX to wait indefinitely, unless there in delay_halt()
196 return 0; in read_current_timer()
215 :"1" (xloops), "0" (lpj * (HZ / 4))); in __const_udelay()
223 __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */ in __udelay()
229 __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */ in __ndelay()
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| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
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| /openbmc/linux/drivers/net/wireless/realtek/rtw88/ |
| H A D | main.c | 92 {.bitrate = 10, .hw_value = 0x00,},
93 {.bitrate = 20, .hw_value = 0x01,},
94 {.bitrate = 55, .hw_value = 0x02,},
95 {.bitrate = 110, .hw_value = 0x03,},
96 {.bitrate = 60, .hw_value = 0x04,},
97 {.bitrate = 90, .hw_value = 0x05,},
98 {.bitrate = 120, .hw_value = 0x06,},
99 {.bitrate = 180, .hw_value = 0x07,},
100 {.bitrate = 240, .hw_value = 0x08,},
101 {.bitrate = 360, .hw_value = 0x09,},
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/book3s/64/ |
| H A D | mmu-hash.h | 34 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
41 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
42 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
43 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
44 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
45 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
46 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
47 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
48 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
49 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
[all …]
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| /openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/ |
| H A D | rtl8xxxu_8192f.c | 34 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10},
35 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01},
36 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08},
37 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08},
38 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10},
39 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00},
40 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10},
41 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00},
42 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20},
43 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e},
[all …]
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| /openbmc/linux/drivers/perf/hisilicon/ |
| H A D | hns3_pmu.c | 29 #define HNS3_PMU_REG_GLOBAL_CTRL 0x0000
30 #define HNS3_PMU_REG_CLOCK_FREQ 0x0020
31 #define HNS3_PMU_REG_BDF 0x0fe0
32 #define HNS3_PMU_REG_VERSION 0x0fe4
33 #define HNS3_PMU_REG_DEVICE_ID 0x0fe8
35 #define HNS3_PMU_REG_EVENT_OFFSET 0x1000
36 #define HNS3_PMU_REG_EVENT_SIZE 0x1000
37 #define HNS3_PMU_REG_EVENT_CTRL_LOW 0x00
38 #define HNS3_PMU_REG_EVENT_CTRL_HIGH 0x04
39 #define HNS3_PMU_REG_EVENT_INTR_STATUS 0x08
[all …]
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