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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt39 - #size-cells: Must be <0>.
53 tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
55 reg = <0x00000001 0x00000000 0x00000400>,
56 <0x00000001 0x00000460 0x00000020>,
57 <0x00000001 0x00000480 0x00000020>,
58 <0x00000001 0x000004A0 0x00000008>,
59 <0x00000001 0x00000400 0x00000020>,
60 <0x00000001 0x00000420 0x00000020>;
63 interrupts = <0 41 4>, <0 40 4>;
77 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvega10_ip_offset.h38 …t struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400…
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } } } };
43 …t struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400…
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } } } };
[all …]
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.h14 #define DDRSS_SS_ID_REV_REG 0x00000000
15 #define DDRSS_SS_CTL_REG 0x00000004
16 #define DDRSS_V2H_CTL_REG 0x00000020
18 #define SS_CTL_REG_CTL_ARST_SHIFT 0x0
22 #define DDRSS_DDRCTL_MSTR 0x00000000
23 #define DDRSS_DDRCTL_STAT 0x00000004
24 #define DDRSS_DDRCTL_MRCTRL0 0x00000010
25 #define DDRSS_DDRCTL_MRCTRL1 0x00000014
26 #define DDRSS_DDRCTL_MRSTAT 0x00000018
27 #define DDRSS_DDRCTL_MRCTRL2 0x0000001C
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]
H A Dbnx2.h30 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
40 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
57 #define RX_BD_FLAGS_NOPUSH (1<<0)
71 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
279 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
321 #define BNX2_L2CTX_TYPE 0x00000000
322 #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
323 #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
324 #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
327 #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
[all …]