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12

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h11 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
13 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
15 {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
16 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
17 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
18 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
21 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
23 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
26 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dhsw_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x00000160,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
H A Divb_clear_kernel.c9 0x00000001, 0x26020128, 0x00000024, 0x00000000,
10 0x00000040, 0x20280c21, 0x00000028, 0x00000001,
11 0x01000010, 0x20000c20, 0x0000002c, 0x00000000,
12 0x00010220, 0x34001c00, 0x00001400, 0x0000002c,
13 0x00600001, 0x20600061, 0x00000000, 0x00000000,
14 0x00000008, 0x20601c85, 0x00000e00, 0x0000000c,
15 0x00000005, 0x20601ca5, 0x00000060, 0x00000001,
16 0x00000008, 0x20641c85, 0x00000e00, 0x0000000d,
17 0x00000005, 0x20641ca5, 0x00000064, 0x00000003,
18 0x00000041, 0x207424a5, 0x00000064, 0x00000034,
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5271.h12 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
15 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
16 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
17 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
18 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
19 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
20 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
21 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
H A Dimmap_5282.h11 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
12 #define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040)
13 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
14 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
15 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140)
16 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180)
17 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0)
18 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
19 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
20 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
H A Dimmap_5275.h13 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
14 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
15 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
16 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
17 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
18 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
19 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
20 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
21 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
22 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
H A Dimmap_5235.h12 #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
13 #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
14 #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
15 #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
16 #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
17 #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
18 #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
19 #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
20 #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
21 #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
[all …]
/openbmc/linux/include/video/
H A Dneomagic.h11 #define NEO_BS0_BLT_BUSY 0x00000001
12 #define NEO_BS0_FIFO_AVAIL 0x00000002
13 #define NEO_BS0_FIFO_PEND 0x00000004
15 #define NEO_BC0_DST_Y_DEC 0x00000001
16 #define NEO_BC0_X_DEC 0x00000002
17 #define NEO_BC0_SRC_TRANS 0x00000004
18 #define NEO_BC0_SRC_IS_FG 0x00000008
19 #define NEO_BC0_SRC_Y_DEC 0x00000010
20 #define NEO_BC0_FILL_PAT 0x00000020
21 #define NEO_BC0_SRC_MONO 0x00000040
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt39 - #size-cells: Must be <0>.
53 tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
55 reg = <0x00000001 0x00000000 0x00000400>,
56 <0x00000001 0x00000460 0x00000020>,
57 <0x00000001 0x00000480 0x00000020>,
58 <0x00000001 0x000004A0 0x00000008>,
59 <0x00000001 0x00000400 0x00000020>,
60 <0x00000001 0x00000420 0x00000020>;
63 interrupts = <0 41 4>, <0 40 4>;
77 #size-cells = <0>;
[all …]
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c19 #define DEV_CS0_BASE 0xe0000000
20 #define DEV_CS1_BASE 0xe1000000
21 #define DEV_CS2_BASE 0xe2000000
22 #define DEV_CS3_BASE 0xe3000000
26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clksrc.h15 #define CLK_MPU_HSI 0x00000200
16 #define CLK_MPU_HSE 0x00000201
17 #define CLK_MPU_PLL1P 0x00000202
18 #define CLK_MPU_PLL1P_DIV 0x00000203
20 #define CLK_AXI_HSI 0x00000240
21 #define CLK_AXI_HSE 0x00000241
22 #define CLK_AXI_PLL2P 0x00000242
24 #define CLK_MCU_HSI 0x00000480
25 #define CLK_MCU_HSE 0x00000481
26 #define CLK_MCU_CSI 0x00000482
[all …]
/openbmc/u-boot/board/Synology/ds414/
H A Dds414.c24 #define DS414_GPP_OUT_VAL_HIGH (0)
26 #define DS414_GPP_OUT_POL_LOW (0)
27 #define DS414_GPP_OUT_POL_MID (0)
28 #define DS414_GPP_OUT_POL_HIGH (0)
33 #define DS414_GPP_OUT_ENA_HIGH (~0)
36 0x11111111,
37 0x22221111,
38 0x22222222,
39 0x00000000,
40 0x11110000,
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c14 #define GUTS_PORDEVSR_OFFS 0xc
15 #define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
19 #define FSL_SRDSCR0_OFFS 0x0
20 #define FSL_SRDSCR0_TXEQA_MASK 0x00007000
21 #define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
22 #define FSL_SRDSCR0_TXEQA_SATA 0x00001000
23 #define FSL_SRDSCR0_TXEQE_MASK 0x00000700
24 #define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
25 #define FSL_SRDSCR0_TXEQE_SATA 0x00000100
28 #define FSL_SRDSCR1_OFFS 0x4
[all …]
/openbmc/u-boot/drivers/misc/
H A Dmpc83xx_serdes.h8 * enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
26 SRDSCR0_TXEQA_MASK = 0x00007000,
27 SRDSCR0_TXEQA_SATA = 0x00001000,
28 SRDSCR0_TXEQE_MASK = 0x00000700,
29 SRDSCR0_TXEQE_SATA = 0x00000100,
69 SRDSCR2_VDD_1V2 = 0x00800000,
71 SRDSCR2_SEICA_MASK = 0x00001c00,
72 SRDSCR2_SEICE_MASK = 0x0000001c,
75 SRDSCR2_SEICA_SATA = 0x00001400,
76 SRDSCR2_SEICE_SATA = 0x00000014,
[all …]
/openbmc/u-boot/board/theadorable/
H A Dtheadorable.c25 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
27 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
29 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
30 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
31 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
33 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
34 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
35 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
43 #define STM_I2C_ADDR 0x27
48 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-firmware.c17 #define CX18_PROC_SOFT_RESET 0xc70010
18 #define CX18_DDR_SOFT_RESET 0xc70014
19 #define CX18_CLOCK_SELECT1 0xc71000
20 #define CX18_CLOCK_SELECT2 0xc71004
21 #define CX18_HALF_CLOCK_SELECT1 0xc71008
22 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
23 #define CX18_CLOCK_POLARITY1 0xc71010
24 #define CX18_CLOCK_POLARITY2 0xc71014
25 #define CX18_ADD_DELAY_ENABLE1 0xc71018
26 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h18 #define BR0 0x5000 /* Register offset to immr */
19 #define BR1 0x5008
20 #define BR2 0x5010
21 #define BR3 0x5018
22 #define BR4 0x5020
23 #define BR5 0x5028
24 #define BR6 0x5030
25 #define BR7 0x5038
27 #define BR_BA 0xFFFF8000
29 #define BR_XBA 0x00006000
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
H A Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/qemu/target/ppc/
H A Dcpu_init.c72 0x00000000); in register_745_sprs()
76 0x00000000); in register_745_sprs()
80 0x00000000); in register_745_sprs()
84 0x00000000); in register_745_sprs()
90 0x00000000); in register_745_sprs()
95 0x00000000); in register_745_sprs()
100 0x00000000); in register_745_sprs()
109 0x00000000); in register_755_sprs()
114 0x00000000); in register_755_sprs()
124 KVM_REG_PPC_DABR, 0x00000000); in register_7xx_sprs()
[all …]
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.h14 #define DDRSS_SS_ID_REV_REG 0x00000000
15 #define DDRSS_SS_CTL_REG 0x00000004
16 #define DDRSS_V2H_CTL_REG 0x00000020
18 #define SS_CTL_REG_CTL_ARST_SHIFT 0x0
22 #define DDRSS_DDRCTL_MSTR 0x00000000
23 #define DDRSS_DDRCTL_STAT 0x00000004
24 #define DDRSS_DDRCTL_MRCTRL0 0x00000010
25 #define DDRSS_DDRCTL_MRCTRL1 0x00000014
26 #define DDRSS_DDRCTL_MRSTAT 0x00000018
27 #define DDRSS_DDRCTL_MRCTRL2 0x0000001C
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */
46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */
56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */
59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */
61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */
62 #define SH7750_PTEH_ASID_S 0
65 #define SH7750_PTEL_REGOFS 0x000004 /* offset */
68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */
[all …]

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