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Searched +full:0 +full:x00000001 (Results 1 – 25 of 1041) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dbase.c60 int nr = 0; in nvkm_device_list()
73 .bios = { 0x00000001, nvkm_bios_new },
79 .bios = { 0x00000001, nvkm_bios_new },
80 .bus = { 0x00000001, nv04_bus_new },
81 .clk = { 0x00000001, nv04_clk_new },
82 .devinit = { 0x00000001, nv04_devinit_new },
83 .fb = { 0x00000001, nv04_fb_new },
84 .i2c = { 0x00000001, nv04_i2c_new },
85 .imem = { 0x00000001, nv04_instmem_new },
86 .mc = { 0x00000001, nv04_mc_new },
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c44 { "IBMR", 0x40301680, 0, 0xffffffff, 'x', "I2C Bus Monitor Register" },
45 { "IBMR_SDAS", 0x40301680, 0, 0x00000001, 'x', "SDA Status" },
46 { "IBMR_SCLS", 0x40301680, 1, 0x00000001, 'x', "SDA Status" },
48 { "IDBR", 0x40301688, 0, 0xffffffff, 'x', "I2C Data Buffer Register" },
49 { "IDBR_IDB", 0x40301688, 0, 0x000000ff, 'x', "I2C Data Buffer" },
51 { "ICR", 0x40301690, 0, 0xffffffff, 'x', "I2C Control Register" },
52 { "ICR_START", 0x40301690, 0, 1, 'x', " start bit " },
53 { "ICR_STOP", 0x40301690, 1, 1, 'x', " stop bit " },
54 { "ICR_ACKNAK",0x40301690, 2, 1, 'x', " send ACK(0) or NAK(1)" },
55 { "ICR_TB", 0x40301690, 3, 1, 'x', " transfer byte bit " },
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dclc37d.h27 #define NV_DISP_NOTIFIER 0x00000000
28 #define NV_DISP_NOTIFIER_SIZEOF 0x00000010
29 #define NV_DISP_NOTIFIER__0 0x00000000
30 #define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0
33 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000
34 #define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001
39 #define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000
40 #define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001
41 #define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002
42 #define NV_DISP_NOTIFIER__1 0x00000001
[all …]
H A Dclc37e.h28 #define NVC37E_UPDATE (0x00000200)
30 #define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000)
31 #define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001)
32 #define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C)
33 #define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0
34 #define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210)
35 #define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0
36 #define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214)
37 #define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0
38 #define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218)
[all …]
H A Dclc57d.h27 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208)
28 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0
30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0…
31 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
32 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
33 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
35 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
36 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
38 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
39 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
[all …]
H A Dcl507d.h27 #define NV_DISP_CORE_NOTIFIER_1 0x00000000
28 #define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054
29 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000
30 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0
31 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000
32 #define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001
35 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001
36 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0
37 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000
38 #define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001
[all …]
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/openbmc/u-boot/board/renesas/stout/
H A Dqos.c76 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init_es1()
80 writel(0x80FF1C1E, &s3c->s3cadsplcr); in qos_init_es1()
81 writel(0x1F060505, &s3c->s3crorr); in qos_init_es1()
82 writel(0x1F020100, &s3c->s3cworr); in qos_init_es1()
86 writel(0x00800080, &s3c_qos->s3cqos0); in qos_init_es1()
87 writel(0x22000010, &s3c_qos->s3cqos1); in qos_init_es1()
88 writel(0x22002200, &s3c_qos->s3cqos2); in qos_init_es1()
89 writel(0x2F002200, &s3c_qos->s3cqos3); in qos_init_es1()
90 writel(0x2F002F00, &s3c_qos->s3cqos4); in qos_init_es1()
91 writel(0x22000010, &s3c_qos->s3cqos5); in qos_init_es1()
[all …]
/openbmc/u-boot/board/renesas/lager/
H A Dqos.c74 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init_es1()
78 writel(0x80FF1C1E, &s3c->s3cadsplcr); in qos_init_es1()
79 writel(0x1F060505, &s3c->s3crorr); in qos_init_es1()
80 writel(0x1F020100, &s3c->s3cworr); in qos_init_es1()
84 writel(0x00800080, &s3c_qos->s3cqos0); in qos_init_es1()
85 writel(0x22000010, &s3c_qos->s3cqos1); in qos_init_es1()
86 writel(0x22002200, &s3c_qos->s3cqos2); in qos_init_es1()
87 writel(0x2F002200, &s3c_qos->s3cqos3); in qos_init_es1()
88 writel(0x2F002F00, &s3c_qos->s3cqos4); in qos_init_es1()
89 writel(0x22000010, &s3c_qos->s3cqos5); in qos_init_es1()
[all …]
/openbmc/u-boot/board/renesas/gose/
H A Dqos.c66 #define is_qos_pri_media() 0
72 #define is_qos_pri_normal() 0
78 #define is_qos_pri_gfx() 0
92 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
96 writel(0x00000000, &s3c->s3cadsplcr); in qos_init()
98 writel(0x1F0B0604, &s3c->s3crorr); in qos_init()
99 writel(0x1F0E0705, &s3c->s3cworr); in qos_init()
101 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
102 writel(0x1F0C0A08, &s3c->s3cworr); in qos_init()
104 writel(0x1F0B0B0B, &s3c->s3crorr); in qos_init()
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe00000 0x200000>; /* 2MB */
100 pinctrl-0 = <&state_default>;
144 nvidia,lock = <0>;
145 nvidia,io-reset = <0>;
[all …]
/openbmc/u-boot/board/renesas/alt/
H A Dqos.c67 #define is_qos_pri_media() 0
73 #define is_qos_pri_normal() 0
79 #define is_qos_pri_gfx() 0
93 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
98 writel(0x1F0B0604, &s3c->s3crorr); in qos_init()
99 writel(0x1F0E0705, &s3c->s3cworr); in qos_init()
101 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
102 writel(0x1F0E0A08, &s3c->s3cworr); in qos_init()
104 writel(0x1F0B0B0B, &s3c->s3crorr); in qos_init()
105 writel(0x1F0E0C0C, &s3c->s3cworr); in qos_init()
[all …]
/openbmc/u-boot/board/renesas/koelsch/
H A Dqos.c104 #define is_qos_pri_media() 0
110 #define is_qos_pri_normal() 0
116 #define is_qos_pri_gfx() 0
130 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
131 writel(0x20042004, DBSC3_1_DBADJ2); in qos_init()
137 /* writel(0x00000000, &s3c->s3cadsplcr); */ in qos_init()
138 /* Linear Linear 0x7000 to 0x7800 mode */ in qos_init()
139 writel(0x00BF1B0C, &s3c->s3cadsplcr); in qos_init()
140 /* Split Linear 0x6800 t 0x7000 mode */ in qos_init()
141 /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ in qos_init()
[all …]
/openbmc/u-boot/board/renesas/silk/
H A Dqos.c76 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
80 writel(0x1F0D0B0A, &s3c->s3crorr); in qos_init()
81 writel(0x1F0D0B09, &s3c->s3cworr); in qos_init()
85 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
86 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
87 writel(0x20302030, &s3c_qos->s3cqos2); in qos_init()
88 writel(0x20AA2200, &s3c_qos->s3cqos3); in qos_init()
89 writel(0x00002032, &s3c_qos->s3cqos4); in qos_init()
90 writel(0x20960010, &s3c_qos->s3cqos5); in qos_init()
91 writel(0x20302030, &s3c_qos->s3cqos6); in qos_init()
[all …]
/openbmc/u-boot/board/renesas/porter/
H A Dqos.c113 writel(0x20042004, DBSC3_0_DBADJ2); in qos_init()
114 writel(0x20042004, DBSC3_1_DBADJ2); in qos_init()
120 /* writel(0x00000000, &s3c->s3cadsplcr); */ in qos_init()
121 /* Linear Linear 0x7000 to 0x7800 mode */ in qos_init()
122 writel(0x00BF1B0C, &s3c->s3cadsplcr); in qos_init()
123 /* Split Linear 0x6800 t 0x7000 mode */ in qos_init()
124 /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */ in qos_init()
126 /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */ in qos_init()
127 writel(0x1F0B0908, &s3c->s3crorr); in qos_init()
128 writel(0x1F0C0A08, &s3c->s3cworr); in qos_init()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
H A Dsoc21_enum.h55 DSM_DATA_SEL_DISABLE = 0x00000000,
56 DSM_DATA_SEL_0 = 0x00000001,
57 DSM_DATA_SEL_1 = 0x00000002,
58 DSM_DATA_SEL_BOTH = 0x00000003,
66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
[all …]
H A Dnavi10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 GATCL1_TYPE_NORMAL = 0x00000000,
185 GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186 GATCL1_TYPE_BYPASS = 0x00000002,
194 UTCL1_TYPE_NORMAL = 0x00000000,
195 UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196 UTCL1_TYPE_BYPASS = 0x00000002,
204 UTCL1_XNACK_SUCCESS = 0x00000000,
205 UTCL1_XNACK_RETRY = 0x00000001,
206 UTCL1_XNACK_PRT = 0x00000002,
[all …]
/openbmc/u-boot/board/renesas/blanche/
H A Dqos.c72 writel(0x20082004, DBSC3_0_DBADJ2); in qos_init()
76 // writel(0x00000000, &s3c->s3cadsplcr); in qos_init()
77 writel(0x1F0D0C0C, &s3c->s3crorr); in qos_init()
78 writel(0x1F1F0C0C, &s3c->s3cworr); in qos_init()
82 writel(0x00890089, &s3c_qos->s3cqos0); in qos_init()
83 writel(0x20960010, &s3c_qos->s3cqos1); in qos_init()
84 writel(0x20302030, &s3c_qos->s3cqos2); in qos_init()
85 writel(0x20AA2200, &s3c_qos->s3cqos3); in qos_init()
86 writel(0x00002032, &s3c_qos->s3cqos4); in qos_init()
87 writel(0x20960010, &s3c_qos->s3cqos5); in qos_init()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxgf110.c32 { 0x001000, 1, 0x01, 0x00000004 },
33 { 0x0000a9, 1, 0x01, 0x0000ffff },
34 { 0x000038, 1, 0x01, 0x0fac6881 },
35 { 0x00003d, 1, 0x01, 0x00000001 },
36 { 0x0000e8, 8, 0x01, 0x00000400 },
37 { 0x000078, 8, 0x01, 0x00000300 },
38 { 0x000050, 1, 0x01, 0x00000011 },
39 { 0x000058, 8, 0x01, 0x00000008 },
40 { 0x000208, 8, 0x01, 0x00000001 },
41 { 0x000081, 1, 0x01, 0x00000001 },
[all …]
H A Dctxgf108.c34 { 0x001000, 1, 0x01, 0x00000004 },
35 { 0x0000a9, 1, 0x01, 0x0000ffff },
36 { 0x000038, 1, 0x01, 0x0fac6881 },
37 { 0x00003d, 1, 0x01, 0x00000001 },
38 { 0x0000e8, 8, 0x01, 0x00000400 },
39 { 0x000078, 8, 0x01, 0x00000300 },
40 { 0x000050, 1, 0x01, 0x00000011 },
41 { 0x000058, 8, 0x01, 0x00000008 },
42 { 0x000208, 8, 0x01, 0x00000001 },
43 { 0x000081, 1, 0x01, 0x00000001 },
[all …]

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