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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c49 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
50 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
51 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
54 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
55 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
56 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
57 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
58 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
H A Dsi.c61 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
62 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
63 mmDB_DEBUG, 0xffffffff, 0x00000000,
64 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
65 mmDB_DEBUG3, 0x0002021c, 0x00020200,
66 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
67 0x340c, 0x000000c0, 0x00800040,
68 0x360c, 0x000000c0, 0x00800040,
69 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
70 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
H A Dgmc_v8_0.c68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
[all …]
H A Dgmc_v7_0.c62 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
63 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
64 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
65 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
69 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
74 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers()
97 WREG32(mmBIF_FB_EN, 0); in gmc_v7_0_mc_stop()
100 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_stop()
113 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v7_0_mc_resume()
116 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v7_0_mc_resume()
[all …]
H A Dgmc_v6_0.c55 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
56 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
57 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
58 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
59 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
60 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
61 #define MC_SEQ_MISC0__MT__HBM 0x60000000
62 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
73 WREG32(mmBIF_FB_EN, 0); in gmc_v6_0_mc_stop()
76 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v6_0_mc_stop()
[all …]
/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Imagine for use with the Onyx (PCX-U) CPU interface
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
[all …]
/openbmc/u-boot/include/configs/
H A Drk3288_common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #include "rockchip-common.h"
17 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
21 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
23 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000
24 #define CONFIG_SYS_LOAD_ADDR 0x00800800
25 #define CONFIG_SPL_STACK 0xff718000
27 # define CONFIG_SPL_TEXT_BASE 0x0
29 # define CONFIG_SPL_TEXT_BASE 0xff704000
37 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
[all …]
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * It can be changed with DIP switch(S2-5).
9 * phys address | S2-5 = OFF | S2-5 = ON
10 * -----------------------------+---------------+---------------
11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
[all …]
/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/
H A Dps7_init_gpl.c1 // SPDX-License-Identifier: GPL-2.0
9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
[all …]
/openbmc/linux/drivers/scsi/mpi3mr/mpi/
H A Dmpi30_transport.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2016-2023 Broadcom Inc. All rights reserved.
20 #define MPI3_VERSION_MINOR (0)
22 #define MPI3_VERSION_DEV (0)
23 #define MPI3_DEVHANDLE_INVALID (0xffff)
73 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
74 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
75 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
77 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
78 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
30 "#address-cells":
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h1 /* SPDX-License-Identifier: MIT */
5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
[all …]
/openbmc/linux/arch/mips/include/asm/mach-malta/
H A Dspaces.h17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
/openbmc/linux/arch/mips/pic32/pic32mzda/
H A Dconfig.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <asm/mach-pic32/pic32.h>
14 #define PIC32_CFGCON 0x0000
15 #define PIC32_DEVID 0x0020
16 #define PIC32_SYSKEY 0x0030
17 #define PIC32_CFGEBIA 0x00c0
18 #define PIC32_CFGEBIC 0x00d0
19 #define PIC32_CFGCON2 0x00f0
20 #define PIC32_RCON 0x1240
49 return 0; in pic32_conf_modify_atomic()
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr10 - SH7785 (SH-4A)
11 - DDR2-SDRAM 512MB
12 - NOR Flash 64MB
13 - 2D Graphic controller
14 - SATA controller
15 - Ethernet controller
16 - USB host/peripheral controller
17 - SD controller
18 - I2C controller
19 - RTC
[all …]
/openbmc/estoraged/src/erase/
H A Dsanitize.cpp8 #include <phosphor-logging/lg2.hpp>
24 constexpr uint32_t mmcSwitchModeWriteByte = 0x03;
26 constexpr uint32_t extCsdCmdSetNormal = (1 << 0);
28 constexpr uint32_t mmcRspPresent = (1 << 0);
33 constexpr uint32_t mmcCmdAc = (0 << 5);
76 uint64_t sectorSize = 0x200; // default value see eMMC spec 6.6.34. in emmcErase()
77 // NOTE: 0x200 is only valid for eMMC greater in emmcErase()
82 eraseCmd.cmds[0].opcode = mmcEraseGroupStart; in emmcErase()
83 eraseCmd.cmds[0].arg = 0; in emmcErase()
84 eraseCmd.cmds[0].flags = mmcRspSpiR1 | mmcRspR1 | mmcCmdAc; in emmcErase()
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dssi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
23 u8 resv0[0x4];
25 u8 resv1[0x8];
34 #define SSI_CR_CIS (0x00000200)
35 #define SSI_CR_TCH (0x00000100)
36 #define SSI_CR_MCE (0x00000080)
37 #define SSI_CR_I2S_MASK (0xFFFFFF9F)
38 #define SSI_CR_I2S_SLAVE (0x00000040)
[all …]
/openbmc/u-boot/drivers/dma/
H A DMCD_tasksInit.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
18 /* Task 0 */
27 MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ in MCD_startDmaChainNoEu()
28 MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ in MCD_startDmaChainNoEu()
30 MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ in MCD_startDmaChainNoEu()
31 MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ in MCD_startDmaChainNoEu()
32 MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ in MCD_startDmaChainNoEu()
33 MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */ in MCD_startDmaChainNoEu()
34 MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ in MCD_startDmaChainNoEu()
[all …]
/openbmc/linux/drivers/soc/aspeed/
H A Daspeed-p2a-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
28 #include <linux/aspeed-p2a-ctrl.h>
30 #define DEVICE_NAME "aspeed-p2a-ctrl"
33 #define SCU2C 0x2c
35 #define SCU180 0x180
36 /* Bit 1 controls the P2A bridge, while bit 0 controls the entire VGA device
91 regmap_update_bits(p2a_ctrl->regmap, in aspeed_p2a_enable_bridge()
97 regmap_update_bits(p2a_ctrl->regmap, SCU180, SCU180_ENP2A, 0); in aspeed_p2a_disable_bridge()
104 struct aspeed_p2a_user *priv = file->private_data; in aspeed_p2a_mmap()
105 struct aspeed_p2a_ctrl *ctrl = priv->parent; in aspeed_p2a_mmap()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dohci.h5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
7 * usb-ohci.h
44 #define ED_NEW 0x00
45 #define ED_UNLINK 0x01
46 #define ED_OPER 0x02
47 #define ED_DEL 0x04
48 #define ED_URB_DEL 0x08
75 #define TD_CC 0xf0000000
76 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
77 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h1 /* SPDX-License-Identifier: MIT */
3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
[all …]
/openbmc/linux/sound/pci/ctxfi/
H A Dcthw20k2.c1 // SPDX-License-Identifier: GPL-2.0-only
48 #define SRCCTL_STATE 0x00000007
49 #define SRCCTL_BM 0x00000008
50 #define SRCCTL_RSR 0x00000030
51 #define SRCCTL_SF 0x000001C0
52 #define SRCCTL_WR 0x00000200
53 #define SRCCTL_PM 0x00000400
54 #define SRCCTL_ROM 0x00001800
55 #define SRCCTL_VO 0x00002000
56 #define SRCCTL_ST 0x00004000
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2007-2011, Intel Corporation.
44 * to the different groups of PowerVR 5-series chip designs
46 * 0x8086 = Intel Corporation
48 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
49 * PowerVR SGX535 - Moorestown - Intel GMA 600
50 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
51 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
57 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
46 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, in nv50_gr_object_bind()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
72 struct nv50_gr *gr = nv50_gr_chan(object)->gr; in nv50_gr_chan_bind()
73 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, in nv50_gr_chan_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
[all …]
/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
24 #define MAX_SPRS (0x10000)
27 #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
41 #define SPR_VR (SPRGROUP_SYS + 0)
70 #define SPR_DMMUCR (SPRGROUP_DMMU + 0)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
[all …]

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