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Searched +full:0 +full:b00000000 (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dpci.txt50 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
61 0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
81 reg = <0x00000800 0 0 0 0>;
/openbmc/linux/fs/9p/
H A Dv9fs.h34 V9FS_PROTO_2000U = 0x01,
35 V9FS_PROTO_2000L = 0x02,
36 V9FS_ACCESS_SINGLE = 0x04,
37 V9FS_ACCESS_USER = 0x08,
38 V9FS_ACCESS_CLIENT = 0x10,
39 V9FS_POSIX_ACL = 0x20,
40 V9FS_NO_XATTR = 0x40,
41 V9FS_IGNORE_QV = 0x80, /* ignore qid.version for cache hints */
42 V9FS_DIRECT_IO = 0x100,
43 V9FS_SYNC = 0x200
[all …]
/openbmc/linux/Documentation/filesystems/
H A D9p.rst86 0b00000000 all caches disabled, mmap disabled
87 0b00000001 file caches enabled
88 0b00000010 meta-data caches enabled
89 0b00000100 writeback behavior (as opposed to writethrough)
90 0b00001000 loose caches (no explicit consistency with server)
91 0b10000000 fscache enabled for persistent caching
97 none 0b00000000 (no caching)
98 readahead 0b00000001 (only read-ahead file caching)
99 mmap 0b00000101 (read-ahead + writeback file cache)
100 loose 0b00001111 (non-coherent file and meta-data caches)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml40 BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be
63 reg = <0x0 0x40000000 0x0 0x1000000>;
64 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
70 iommu-map = <0x0 &iommu0 0x0 0x8
71 0x9 &iommu0 0x9 0xfff7>;
74 iommu0: iommu@1,0 {
76 reg = <0x800 0 0 0 0>;
85 reg = <0x0 0x50000000 0x0 0x1000000>;
86 ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>;
90 * with endpoint IDs 0x10000 - 0x1ffff
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddpp.h74 { 0x2000, 0, 0, 0,
75 0, 0x2000, 0, 0,
76 0, 0, 0x2000, 0 } },
78 { 0x2000, 0, 0, 0,
79 0, 0x2000, 0, 0,
80 0, 0, 0x2000, 0 } },
82 { 0x2cdd, 0x2000, 0, 0xe991,
83 0xe926, 0x2000, 0xf4fd, 0x10ef,
84 0, 0x2000, 0x38b4, 0xe3a6 } },
86 { 0x3353, 0x2568, 0, 0xe400,
[all …]
/openbmc/qemu/hw/char/
H A Davr_usart.c34 return 0; in avr_usart_can_receive()
44 usart->data = buffer[0]; in avr_usart_receive()
54 uint8_t mode = ((usart->csrc & USART_CSRC_CSZ0) ? 1 : 0) | in update_char_mask()
55 ((usart->csrc & USART_CSRC_CSZ1) ? 2 : 0) | in update_char_mask()
56 ((usart->csrb & USART_CSRB_CSZ2) ? 4 : 0); in update_char_mask()
58 case 0: in update_char_mask()
59 usart->char_mask = 0b11111; in update_char_mask()
62 usart->char_mask = 0b111111; in update_char_mask()
65 usart->char_mask = 0b1111111; in update_char_mask()
68 usart->char_mask = 0b11111111; in update_char_mask()
[all …]
/openbmc/linux/arch/x86/crypto/
H A Dsm3-avx-asm_64.S20 #define state_h0 0
33 #define K0 2043430169 /* 0x79cc4519 */
34 #define K1 -208106958 /* 0xf3988a32 */
35 #define K2 -416213915 /* 0xe7311465 */
36 #define K3 -832427829 /* 0xce6228cb */
37 #define K4 -1664855657 /* 0x9cc45197 */
38 #define K5 965255983 /* 0x3988a32f */
39 #define K6 1930511966 /* 0x7311465e */
40 #define K7 -433943364 /* 0xe6228cbc */
41 #define K8 -867886727 /* 0xcc451979 */
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dtvaudio.c161 if (subaddr < 0) { in chip_write()
162 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val); in chip_write()
164 buffer[0] = val; in chip_write()
167 v4l2_warn(sd, "I/O error (write 0x%x)\n", val); in chip_write()
168 if (rc < 0) in chip_write()
180 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n", in chip_write()
183 buffer[0] = subaddr; in chip_write()
187 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n", in chip_write()
189 if (rc < 0) in chip_write()
194 return 0; in chip_write()
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc150 TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
544 tcg_gen_movi_i64(t0, 0);
582 #define SGN_MASK_DP 0x8000000000000000ull
583 #define SGN_MASK_SP 0x8000000080000000ull
584 #define EXP_MASK_DP 0x7FF0000000000000ull
585 #define EXP_MASK_SP 0x7F8000007F800000ull
624 set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
720 0
769 0
971 set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \
[all …]