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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.2-job-ring",
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H A Dqoriq-sec5.3-0.dtsi2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
[all …]
H A Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
[all …]
H A Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
[all …]
H A Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
45 compatible = "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
[all …]
H A Dp1023si-post.dtsi4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
40 - items:
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/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dls102xa_stream_id.h1 /* SPDX-License-Identifier: GPL-2.0+ */
27 * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
30 SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
33 CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
34 SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
37 CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
39 /* This is a bit evil since we treat rtic param as both a string & hex value */
40 #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ argument
41 SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
43 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_liodn.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
35 + (port - 1) * 0x200 \
70 { .compat[0] = name1, \
101 SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
113 /* reg nodes for DMA start @ 0x300 */
116 CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
[all …]
/openbmc/u-boot/include/
H A Dfsl_sec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
34 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
35 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
55 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
59 u32 rttotsam; /* PRGM=0: total samples register */
65 u32 rtfreqcnt; /* PRGM=0: freq. count register */
68 #define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
69 #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
79 u8 res1[0x4];
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/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #include <asm/arch/imx-regs.h>
17 #include <generated/asm-offsets.h>
21 * AIPS setup - Only setup MPROTx registers.
25 * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
26 * user-mode.
28 .macro init_aips mpr=0x77777777
39 * MAX (Multi-Layer AHB Crossbar Switch) setup
42 * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
43 * - SGPCR: always park on last master
[all …]
/openbmc/linux/drivers/crypto/caam/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #define CCM_MPCTL 0x00
21 #define CCM_UPCTL 0x04
22 #define CCM_CCTL 0x08
23 #define CCM_CGCR0 0x0C
24 #define CCM_CGCR1 0x10
25 #define CCM_CGCR2 0x14
26 #define CCM_PCDR0 0x18
27 #define CCM_PCDR1 0x1C
28 #define CCM_PCDR2 0x20
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos5420.h>
12 #include <linux/clk-provider.h>
18 #include "clk-cpu.h"
19 #include "clk-exynos5-subcmu.h"
21 #define APLL_LOCK 0x0
22 #define APLL_CON0 0x100
23 #define SRC_CPU 0x200
24 #define DIV_CPU0 0x500
25 #define DIV_CPU1 0x504
[all …]