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/openbmc/linux/arch/arm/mach-davinci/
H A Dda850.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DA850/OMAP-L138 chip specific setup
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
7 * Derived from: arch/arm/mach-davinci/da830.c
16 #include <linux/mfd/da8xx-cfgchip.h>
20 #include <clocksource/timer-davinci.h>
32 #define DA850_PLL1_BASE 0x01e1a000
33 #define DA850_TIMER64P2_BASE 0x01f0c000
34 #define DA850_TIMER64P3_BASE 0x01f0d000
47 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
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/openbmc/linux/arch/powerpc/crypto/
H A Daes-gcm-p10.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
57 vcipher 15, 15, 19
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/openbmc/linux/include/linux/mfd/wm831x/
H A Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
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H A Dregulator.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x
14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
18 #define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
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/openbmc/entity-manager/configurations/meta/
H A Dyosemite4_sentineldome_t2_retimer.json9 "ICoefficient": -0.02,
11 "ILimitMin": -50,
14 "SENTINEL_DOME_SLOT $bus % 15 MB_X8_RTM_TEMP_C"
16 "Name": "PID_MB_RETIMER_TEMP_Slot $bus % 15",
19 "OutLimitMin": 0,
20 "PCoefficient": -5.0,
36 "ICoefficient": -0.035,
38 "ILimitMin": -50,
41 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A0_TEMP_C",
42 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A1_TEMP_C",
[all …]
H A Dyosemite4_sentineldome_t1_retimer.json9 "ICoefficient": -0.02,
11 "ILimitMin": -50,
14 "SENTINEL_DOME_SLOT $bus % 15 MB_X8_RTM_TEMP_C"
16 "Name": "PID_MB_RETIMER_TEMP_Slot $bus % 15",
19 "OutLimitMin": 0,
20 "PCoefficient": -5.0,
36 "ICoefficient": -0.035,
38 "ILimitMin": -50,
41 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A0_TEMP_C",
42 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A1_TEMP_C",
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H A Dyosemite4_sentineldome_t2.json9 "ICoefficient": -0.035,
11 "ILimitMin": -50,
14 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A0_TEMP_C",
15 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A1_TEMP_C",
16 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A2_TEMP_C",
17 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A3_TEMP_C",
18 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A4_TEMP_C",
19 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A5_TEMP_C",
20 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A6_TEMP_C",
21 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A7_TEMP_C",
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H A Dyosemite4_wailuafalls.json9 "ICoefficient": -0.02,
11 "ILimitMin": -50,
14 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC1_P0V8_TEMP_C",
15 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC1_PVDDQ_CD_TEMP_C",
16 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC1_P0V85_TEMP_C",
17 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC1_PVDDQ_AB_TEMP_C",
18 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC2_P0V8_TEMP_C",
19 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC2_PVDDQ_CD_TEMP_C",
20 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC2_P0V85_TEMP_C",
21 "WAILUA_FALLS_SLOT $bus % 15 WF_VR_ASIC2_PVDDQ_AB_TEMP_C"
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H A Dyosemite4_sentineldome_t1.json9 "ICoefficient": -0.035,
11 "ILimitMin": -50,
14 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A0_TEMP_C",
15 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A1_TEMP_C",
16 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A2_TEMP_C",
17 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A3_TEMP_C",
18 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A4_TEMP_C",
19 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A6_TEMP_C",
20 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A7_TEMP_C",
21 "SENTINEL_DOME_SLOT $bus % 15 DIMM_A8_TEMP_C",
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H A Dminerva_fanboard_adc_silergy.json5 "Address": "0x5e",
8 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_IL",
10 "PwmName": "FCB_$bus - 15 FAN_PWM",
12 0 number
15 "Index": 0,
16 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_IL_SPEED_RPM",
37 "Address": "0x5e",
40 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_OL",
42 "PwmName": "FCB_$bus - 15 FAN_PWM",
48 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_OL_SPEED_RPM",
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H A Dminerva_fanboard_adc_ti.json5 "Address": "0x5e",
8 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_IL",
10 "PwmName": "FCB_$bus - 15 FAN_PWM",
12 0 number
15 "Index": 0,
16 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_IL_SPEED_RPM",
37 "Address": "0x5e",
40 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_OL",
42 "PwmName": "FCB_$bus - 15 FAN_PWM",
48 "Name": "FCB_$bus - 15 FAN $bus * 4 - 64 + 1 TACH_OL_SPEED_RPM",
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/openbmc/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
34 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
46 memset(pps_header, 0, sizeof(*pps_header)); in drm_dsc_dp_pps_header_init()
48 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
49 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
54 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
56 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
59 * buffer size in bytes, or 0 on invalid input
75 return 0; in drm_dsc_dp_rc_buffer_size()
81 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
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/openbmc/linux/tools/testing/selftests/hid/tests/
H A Dtest_tablet.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
23 https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/windows-pen-states
37 def from_evdev(cls, evdev) -> "PenState":
58 def apply(self, events) -> "PenState":
91 def valid_transitions(self) -> Tuple["PenState", ...]:
93 for skipping the in-range state, due to historical reasons.
145 self.tippressure = 15
146 self.azimuth = 0
153 self.x_tilt = 0
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H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = ("hid-multitouch", "hid_multitouch")
28 "NOT_SEEN_MEANS_UP": BIT(0),
43 "TOUCH_SIZE_SCALING": BIT(15),
65 self.tippressure = 15
66 self.azimuth = 0
74 super().__init__(0, x, y)
80 self.twist = 0
91 Usage Page (0xff00)
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/openbmc/linux/drivers/infiniband/hw/irdma/
H A Di40iw_hw.h1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
5 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
6 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
7 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
8 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
9 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
10 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
11 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
12 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
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/openbmc/linux/arch/arm64/include/asm/
H A Dapple_m1_pmu.h1 // SPDX-License-Identifier: GPL-2.0
10 #define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0)
11 #define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0)
12 #define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0)
13 #define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0)
14 #define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0)
15 #define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0)
16 #define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0)
17 #define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0)
18 #define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0)
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/openbmc/linux/sound/soc/codecs/
H A Dwm5100.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * wm5100.h -- WM5100 ALSA SoC Audio driver
26 #define WM5100_CLKSRC_MCLK1 0
34 #define WM5100_CLKSRC_ASYNCCLK 0x100
39 #define WM5100_FLL_SRC_MCLK1 0x0
40 #define WM5100_FLL_SRC_MCLK2 0x1
41 #define WM5100_FLL_SRC_FLL1 0x4
42 #define WM5100_FLL_SRC_FLL2 0x5
43 #define WM5100_FLL_SRC_AIF1BCLK 0x8
44 #define WM5100_FLL_SRC_AIF2BCLK 0x9
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H A Dwm9081.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * wm9081.c -- WM9081 ALSA SoC Audio driver
24 #define WM9081_SOFTWARE_RESET 0x00
25 #define WM9081_ANALOGUE_LINEOUT 0x02
26 #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
27 #define WM9081_VMID_CONTROL 0x04
28 #define WM9081_BIAS_CONTROL_1 0x05
29 #define WM9081_ANALOGUE_MIXER 0x07
30 #define WM9081_ANTI_POP_CONTROL 0x08
31 #define WM9081_ANALOGUE_SPEAKER_1 0x09
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/openbmc/u-boot/board/ms7750se/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 modified from SH-IPL+g
17 #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
18 #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
20 #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
21 A3:2 A2:15 A1:15 A0:6 A0B:7 */
23 #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
24 A3:2 A2:15 A1:15 A0:6 A0B:7 */
26 #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
27 A2: 1-3 A1: 1-3 A0: 0-1 */
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/openbmc/linux/arch/s390/include/asm/
H A Dvx-insn-asm.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/vx-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
31 \opd = 0
76 \opd = 15
83 /* VX_NUM - Retrieve vector register number
95 \opd = 0
140 \opd = 15
195 /* RXB - Compute most significant bit used vector registers
203 .macro RXB rxb v1 v2=0 v3=0 v4=0
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/openbmc/phosphor-webui/app/assets/images/
H A Dicon-arrow-gray.svg1 …0 0 30 30"><style>.st0{fill:#aaa}</style><path class="st0" d="M15 2c7.2 0 13 5.8 13 13s-5.8 13-13 …
H A Dicon-arrow-blue.svg1 …0 0 30 30"><style>.st0{fill:#2d60e5}</style><path class="st0" d="M15 2c7.2 0 13 5.8 13 13s-5.8 13-…
/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
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/openbmc/linux/arch/csky/abiv2/inc/abi/
H A Dckmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 return mfcr("cr<0, 15>"); in read_mmu_index()
16 mtcr("cr<0, 15>", value); in write_mmu_index()
21 return mfcr("cr<2, 15>"); in read_mmu_entrylo0()
26 return mfcr("cr<3, 15>"); in read_mmu_entrylo1()
31 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
36 return mfcr("cr<4, 15>"); in read_mmu_entryhi()
41 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
46 return mfcr("cr<30, 15>"); in read_mmu_msa0()
51 mtcr("cr<30, 15>", value); in write_mmu_msa0()
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/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "hw/core/tcg-cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
28 t = cpu->isar.id_isar5; in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
45 cpu->isar.id_isar6 = t; in aa32_max_features()
47 t = cpu->isar.mvfr1; in aa32_max_features()
50 cpu->isar.mvfr1 = t; in aa32_max_features()
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