| /openbmc/linux/Documentation/driver-api/ |
| H A D | reset.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
13 the `consumer driver interface <#consumer-driver-interface>`__ (`API reference
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
[all …]
|
| H A D | socionext,uniphier-reset.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier reset controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - description: System reset
17 - socionext,uniphier-ld4-reset
18 - socionext,uniphier-pro4-reset
19 - socionext,uniphier-sld8-reset
[all …]
|
| H A D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
[all …]
|
| H A D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
6 typically provided by means of memory-mapped I/O registers. These registers are
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
22 --------------------
23 - compatible : Should be,
[all …]
|
| H A D | socionext,uniphier-glue-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier peripheral core reset in glue layer
10 Some peripheral core reset belongs to its own glue layer. Before using
11 this core reset, it is necessary to control the clocks and resets to
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
[all …]
|
| H A D | xlnx,zynqmp-reset.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Zynq UltraScale+ MPSoC and Versal reset
10 - Piyush Mehta <piyush.mehta@amd.com>
15 The PS reset subsystem is responsible for handling the external reset
16 input to the device and that all internal reset requirements are met
19 Please also refer to reset.txt in this directory for common reset
20 controller binding usage. Device nodes that need access to reset
[all …]
|
| H A D | amlogic,meson-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SoC Reset Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
[all …]
|
| /openbmc/linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
[all …]
|
| H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += hisilicon/
4 obj-y += starfive/
5 obj-$(CONFIG_ARCH_STI) += sti/
6 obj-$(CONFIG_ARCH_TEGRA) += tegra/
7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
[all …]
|
| H A D | reset-ti-sci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
19 * @dev_id: SoC-specific device identifier
20 * @reset_mask: reset mask to use for toggling reset
21 * @lock: synchronize reset_mask read-modify-writes
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
[all …]
|
| H A D | reset-ti-syscon.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI SYSCON regmap reset driver
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/ti-syscon.h>
20 * struct ti_syscon_reset_control - reset control structure
21 * @assert_offset: reset assert control register offset from syscon base
22 * @assert_bit: reset assert bit in the reset assert control register
23 * @deassert_offset: reset deassert control register offset from syscon base
24 * @deassert_bit: reset deassert bit in the reset deassert control register
[all …]
|
| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset Controller framework
16 #include <linux/reset.h>
17 #include <linux/reset-controller.h>
27 * struct reset_control - a reset control
28 * @rcdev: a pointer to the reset controller device
29 * this reset control belongs to
30 * @list: list entry for the rcdev's reset controller list
31 * @id: ID of the reset controller in the reset
36 * @array: Is this an array of reset controls (1)?
[all …]
|
| /openbmc/u-boot/include/ |
| H A D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * A reset is a hardware signal indicating that a HW module (or IP block, or
13 * sometimes an entire off-CPU chip) reset all of its internal state to some
14 * known-good initial state. Drivers will often reset HW modules when they
16 * or in response to some error condition. Reset signals are often controlled
17 * externally to the HW module being reset, by an entity this API calls a reset
19 * reset controllers set or clear reset signals.
21 * A driver that implements UCLASS_RESET is a reset controller or provider. A
22 * controller will often implement multiple separate reset signals, since the
23 * hardware it manages often has this capability. reset-uclass.h describes the
[all …]
|
| H A D | sysreset.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 SYSRESET_WARM, /* Reset CPU, keep GPIOs active */
12 SYSRESET_COLD, /* Reset CPU and GPIOs */
13 SYSRESET_POWER, /* Reset PMIC (remove and restore power) */
21 * request() - request a sysreset of the given type
23 * Note that this function may return before the reset takes effect.
25 * @type: Reset type to request
26 * @return -EINPROGRESS if the reset has been started and
27 * will complete soon, -EPROTONOSUPPORT if not supported
28 * by this device, 0 if the reset has already happened
[all …]
|
| /openbmc/linux/drivers/power/reset/ |
| H A D | at91-reset.c | 2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
6 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
28 #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
29 #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */
30 #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */
31 #define AT91_RSTC_EXTRST BIT(3) /* External Reset */
34 #define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
35 #define AT91_RSTC_URSTS BIT(0) /* User Reset Status */
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/reset/ |
| H A D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
[all …]
|
| /openbmc/u-boot/drivers/reset/ |
| H A D | Kconfig | 1 menu "Reset Controller Support"
4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable the sandbox reset test driver"
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
[all …]
|
| H A D | reset-ti-sci.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Texas Instruments System Control Interface (TI SCI) reset driver
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
8 * Loosely based on Linux kernel reset-ti-sci.c...
14 #include <reset-uclass.h>
18 * struct ti_sci_reset_data - reset controller information structure
32 return -ENOMEM; in ti_sci_reset_probe()
35 data->sci = ti_sci_get_handle(dev); in ti_sci_reset_probe()
36 if (IS_ERR(data->sci)) in ti_sci_reset_probe()
37 return PTR_ERR(data->sci); in ti_sci_reset_probe()
[all …]
|
| /openbmc/qemu/docs/devel/ |
| H A D | reset.rst | 3 Reset in QEMU: the Resettable interface
6 The reset of qemu objects is handled using the resettable interface declared
10 whole group can be reset consistently. Each individual member object does not
12 reset first) are addressed.
17 Triggering reset
18 ----------------
24 You can apply a reset to an object using ``resettable_assert_reset()``. You need
25 to call ``resettable_release_reset()`` to release the object from reset. To
26 instantly reset an object, without keeping it in reset state, just call
28 object to reset and a reset type.
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
[all …]
|
| /openbmc/linux/drivers/clk/visconti/ |
| H A D | reset.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti ARM SoC reset controller
16 #include "reset.h"
25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
27 u32 rst = BIT(data->rs_idx); in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
[all …]
|
| /openbmc/linux/include/linux/ |
| H A D | reset.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct reset_control_bulk_data - Data used for bulk reset control operations.
16 * @id: reset control consumer ID
17 * @rstc: struct reset_control * to store the associated reset control
19 * The reset APIs provide a series of reset_control_bulk_*() API calls as
20 * a convenience to consumers which require multiple reset controls.
114 return optional ? 0 : -ENOTSUPP; in __device_reset()
122 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __of_reset_control_get()
130 return optional ? NULL : ERR_PTR(-ENOTSUPP); in __reset_control_get()
167 return optional ? 0 : -EOPNOTSUPP; in __reset_control_bulk_get()
[all …]
|
| /openbmc/linux/drivers/infiniband/hw/irdma/ |
| H A D | i40iw_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
5 #define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
6 #define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
7 #define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
8 #define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
9 #define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
10 #define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
11 #define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
12 #define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
[all …]
|
| /openbmc/u-boot/doc/device-tree-bindings/gpu/ |
| H A D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
7 - #address-cells: The number of cells used to represent physical base addresses
9 - #size-cells: The number of cells used to represent the size of an address
11 - ranges: The mapping of the host1x address space to the CPU address space.
12 - clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
[all …]
|