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/openbmc/u-boot/drivers/gpio/
H A Ds5p_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
14 #include <dm/device-internal.h>
21 #define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2)) argument
22 #define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2)) argument
24 #define DAT_MASK(gpio) (0x1 << (gpio)) argument
25 #define DAT_SET(gpio) (0x1 << (gpio)) argument
27 #define PULL_MASK(gpio) (0x3 << ((gpio) << 1)) argument
28 #define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1)) argument
30 #define DRV_MASK(gpio) (0x3 << ((gpio) << 1)) argument
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H A Domap_gpio.c1 // SPDX-License-Identifier: GPL-2.0
8 * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
13 * linux/arch/arm/plat-omap/gpio.c
15 * Support functions for OMAP GPIO
17 * Copyright (C) 2003-2005 Nokia Corporation
23 #include <asm/gpio.h>
44 static inline int get_gpio_index(int gpio) in get_gpio_index() argument
46 return gpio & 0x1f; in get_gpio_index()
49 int gpio_is_valid(int gpio) in gpio_is_valid() argument
51 return (gpio >= 0) && (gpio < OMAP_MAX_GPIO); in gpio_is_valid()
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H A Dzynq_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq GPIO device driver
7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
8 * Copyright (C) 2009 - 2014 Xilinx, Inc.
12 #include <asm/gpio.h>
44 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
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H A Dkona_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
16 #define GPIO_BANK(gpio) ((gpio) >> 5) argument
17 #define GPIO_BITMASK(gpio) \ argument
18 (1UL << ((gpio) & (GPIO_PER_BANK - 1)))
20 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) argument
21 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) argument
22 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) argument
23 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) argument
24 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) argument
25 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) argument
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H A Dtegra_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra20 GPIO handling.
4 * (C) Copyright 2010-2012,2015
21 #include <asm/gpio.h>
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
31 struct gpio_ctlr_bank *bank; member
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
38 struct gpio_ctlr_bank *bank; member
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H A Daspeed_gpio.c2 * ast_gpio.c - GPIO driver for the Aspeed SoC
10 #include <asm/gpio.h>
146 static inline void __iomem *bank_reg(struct aspeed_gpio_priv *gpio, in bank_reg() argument
147 const struct aspeed_gpio_bank *bank, in bank_reg() argument
152 return gpio->regs + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
154 return gpio->regs + bank->rdata_reg; in bank_reg()
156 return gpio->regs + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
158 return gpio->regs + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
160 return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
162 return gpio->regs + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
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H A Dhi6220_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/gpio.h>
13 static int hi6220_gpio_direction_input(struct udevice *dev, unsigned int gpio) in hi6220_gpio_direction_input() argument
15 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_direction_input() local
18 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
19 data &= ~(1 << gpio); in hi6220_gpio_direction_input()
20 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
25 static int hi6220_gpio_set_value(struct udevice *dev, unsigned gpio, in hi6220_gpio_set_value() argument
28 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_set_value() local
30 writeb(!!value << gpio, bank->base + (BIT(gpio + 2))); in hi6220_gpio_set_value()
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
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H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
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H A Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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/openbmc/linux/drivers/gpio/
H A Dgpio-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 #include <linux/gpio/driver.h>
27 #include <linux/platform_data/gpio-omap.h>
78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
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H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
34 unsigned int bank; member
50 * represents disabled debouncing for the GPIO. Any other value for an element
85 * line even when the GPIO is configured as an output. Since
210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() argument
211 const struct aspeed_gpio_bank *bank, in bank_reg() argument
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H A Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/driver.h>
49 * Note: The "value" register returns the input value when the GPIO is
52 * The "rdata" register returns the output value when the GPIO is
104 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() argument
105 const struct aspeed_sgpio_bank *bank, in bank_reg() argument
110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
112 return gpio->base + bank->rdata_reg; in bank_reg()
114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
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H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
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H A Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM Serial GPIO Driver
10 #include <linux/gpio/driver.h>
137 static void __iomem *bank_reg(struct npcm_sgpio *gpio, in bank_reg() argument
138 const struct npcm_sgpio_bank *bank, in bank_reg() argument
143 return gpio->base + bank->rdata_reg; in bank_reg()
145 return gpio->base + bank->wdata_reg; in bank_reg()
147 return gpio->base + bank->event_config; in bank_reg()
149 return gpio->base + bank->event_status; in bank_reg()
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg()
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H A Dgpio-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-tegra/gpio.c
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
17 #include <linux/gpio/driver.h>
31 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
45 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
46 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
47 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
48 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
49 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
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H A Dgpio-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom Kona GPIO Driver
5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6 * Copyright (C) 2012-2014 Broadcom Corporation
11 #include <linux/gpio/driver.h>
24 #define GPIO_BANK(gpio) ((gpio) >> 5) argument
25 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) argument
27 /* There is a GPIO control register for each GPIO */
28 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) argument
30 /* The remaining registers are per GPIO bank */
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H A Dgpio-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/gpio/driver.h>
22 #include <linux/pinctrl/pinconf-generic.h>
27 #include "../pinctrl/pinctrl-rockchip.h"
29 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
30 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
31 #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
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/openbmc/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
11 echo "GPIO $MODULE test FAIL"
17 echo "GPIO $MODULE test SKIP"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
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/openbmc/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
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/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
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H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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