xref: /openbmc/linux/arch/arm/mach-zynq/slcr.c (revision 9eedb910)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Xilinx SLCR driver
4  *
5  * Copyright (c) 2011-2013 Xilinx Inc.
6  */
7 
8 #include <linux/io.h>
9 #include <linux/reboot.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_address.h>
12 #include <linux/regmap.h>
13 #include <linux/clk/zynq.h>
14 #include "common.h"
15 
16 /* register offsets */
17 #define SLCR_UNLOCK_OFFSET		0x8   /* SCLR unlock register */
18 #define SLCR_PS_RST_CTRL_OFFSET		0x200 /* PS Software Reset Control */
19 #define SLCR_A9_CPU_RST_CTRL_OFFSET	0x244 /* CPU Software Reset Control */
20 #define SLCR_REBOOT_STATUS_OFFSET	0x258 /* PS Reboot Status */
21 #define SLCR_PSS_IDCODE			0x530 /* PS IDCODE */
22 #define SLCR_L2C_RAM			0xA1C /* L2C_RAM in AR#54190 */
23 
24 #define SLCR_UNLOCK_MAGIC		0xDF0D
25 #define SLCR_A9_CPU_CLKSTOP		0x10
26 #define SLCR_A9_CPU_RST			0x1
27 #define SLCR_PSS_IDCODE_DEVICE_SHIFT	12
28 #define SLCR_PSS_IDCODE_DEVICE_MASK	0x1F
29 
30 static void __iomem *zynq_slcr_base;
31 static struct regmap *zynq_slcr_regmap;
32 
33 /**
34  * zynq_slcr_write - Write to a register in SLCR block
35  *
36  * @val:	Value to write to the register
37  * @offset:	Register offset in SLCR block
38  *
39  * Return:	a negative value on error, 0 on success
40  */
zynq_slcr_write(u32 val,u32 offset)41 static int zynq_slcr_write(u32 val, u32 offset)
42 {
43 	return regmap_write(zynq_slcr_regmap, offset, val);
44 }
45 
46 /**
47  * zynq_slcr_read - Read a register in SLCR block
48  *
49  * @val:	Pointer to value to be read from SLCR
50  * @offset:	Register offset in SLCR block
51  *
52  * Return:	a negative value on error, 0 on success
53  */
zynq_slcr_read(u32 * val,u32 offset)54 static int zynq_slcr_read(u32 *val, u32 offset)
55 {
56 	return regmap_read(zynq_slcr_regmap, offset, val);
57 }
58 
59 /**
60  * zynq_slcr_unlock - Unlock SLCR registers
61  *
62  * Return:	a negative value on error, 0 on success
63  */
zynq_slcr_unlock(void)64 static inline int zynq_slcr_unlock(void)
65 {
66 	zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
67 
68 	return 0;
69 }
70 
71 /**
72  * zynq_slcr_get_device_id - Read device code id
73  *
74  * Return:	Device code id
75  */
zynq_slcr_get_device_id(void)76 u32 zynq_slcr_get_device_id(void)
77 {
78 	u32 val;
79 
80 	zynq_slcr_read(&val, SLCR_PSS_IDCODE);
81 	val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
82 	val &= SLCR_PSS_IDCODE_DEVICE_MASK;
83 
84 	return val;
85 }
86 
87 /**
88  * zynq_slcr_system_restart - Restart the entire system.
89  *
90  * @nb:		Pointer to restart notifier block (unused)
91  * @action:	Reboot mode (unused)
92  * @data:	Restart handler private data (unused)
93  *
94  * Return:	0 always
95  */
96 static
zynq_slcr_system_restart(struct notifier_block * nb,unsigned long action,void * data)97 int zynq_slcr_system_restart(struct notifier_block *nb,
98 			     unsigned long action, void *data)
99 {
100 	u32 reboot;
101 
102 	/*
103 	 * Clear 0x0F000000 bits of reboot status register to workaround
104 	 * the FSBL not loading the bitstream after soft-reboot
105 	 * This is a temporary solution until we know more.
106 	 */
107 	zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
108 	zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
109 	zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
110 	return 0;
111 }
112 
113 static struct notifier_block zynq_slcr_restart_nb = {
114 	.notifier_call	= zynq_slcr_system_restart,
115 	.priority	= 192,
116 };
117 
118 /**
119  * zynq_slcr_cpu_start - Start cpu
120  * @cpu:	cpu number
121  */
zynq_slcr_cpu_start(int cpu)122 void zynq_slcr_cpu_start(int cpu)
123 {
124 	u32 reg;
125 
126 	zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
127 	reg &= ~(SLCR_A9_CPU_RST << cpu);
128 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
129 	reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
130 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
131 
132 	zynq_slcr_cpu_state_write(cpu, false);
133 }
134 
135 /**
136  * zynq_slcr_cpu_stop - Stop cpu
137  * @cpu:	cpu number
138  */
zynq_slcr_cpu_stop(int cpu)139 void zynq_slcr_cpu_stop(int cpu)
140 {
141 	u32 reg;
142 
143 	zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
144 	reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
145 	zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
146 }
147 
148 /**
149  * zynq_slcr_cpu_state - Read/write cpu state
150  * @cpu:	cpu number
151  *
152  * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
153  * 0 means cpu is running, 1 cpu is going to die.
154  *
155  * Return: true if cpu is running, false if cpu is going to die
156  */
zynq_slcr_cpu_state_read(int cpu)157 bool zynq_slcr_cpu_state_read(int cpu)
158 {
159 	u32 state;
160 
161 	state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
162 	state &= 1 << (31 - cpu);
163 
164 	return !state;
165 }
166 
167 /**
168  * zynq_slcr_cpu_state - Read/write cpu state
169  * @cpu:	cpu number
170  * @die:	cpu state - true if cpu is going to die
171  *
172  * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
173  * 0 means cpu is running, 1 cpu is going to die.
174  */
zynq_slcr_cpu_state_write(int cpu,bool die)175 void zynq_slcr_cpu_state_write(int cpu, bool die)
176 {
177 	u32 state, mask;
178 
179 	state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
180 	mask = 1 << (31 - cpu);
181 	if (die)
182 		state |= mask;
183 	else
184 		state &= ~mask;
185 	writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
186 }
187 
188 /**
189  * zynq_early_slcr_init - Early slcr init function
190  *
191  * Return:	0 on success, negative errno otherwise.
192  *
193  * Called very early during boot from platform code to unlock SLCR.
194  */
zynq_early_slcr_init(void)195 int __init zynq_early_slcr_init(void)
196 {
197 	struct device_node *np;
198 
199 	np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
200 	if (!np) {
201 		pr_err("%s: no slcr node found\n", __func__);
202 		BUG();
203 	}
204 
205 	zynq_slcr_base = of_iomap(np, 0);
206 	if (!zynq_slcr_base) {
207 		pr_err("%s: Unable to map I/O memory\n", __func__);
208 		BUG();
209 	}
210 
211 	np->data = (__force void *)zynq_slcr_base;
212 
213 	zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
214 	if (IS_ERR(zynq_slcr_regmap)) {
215 		pr_err("%s: failed to find zynq-slcr\n", __func__);
216 		of_node_put(np);
217 		return -ENODEV;
218 	}
219 
220 	/* unlock the SLCR so that registers can be changed */
221 	zynq_slcr_unlock();
222 
223 	/* See AR#54190 design advisory */
224 	regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);
225 
226 	register_restart_handler(&zynq_slcr_restart_nb);
227 
228 	pr_info("%pOFn mapped to %p\n", np, zynq_slcr_base);
229 
230 	of_node_put(np);
231 
232 	return 0;
233 }
234