xref: /openbmc/u-boot/drivers/mtd/nand/raw/zynq_nand.c (revision a1588ac8)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016 Xilinx, Inc.
4  *
5  * Xilinx Zynq NAND Flash Controller Driver
6  * This driver is based on plat_nand.c and mxc_nand.c drivers
7  */
8 
9 #include <common.h>
10 #include <malloc.h>
11 #include <asm/io.h>
12 #include <linux/errno.h>
13 #include <nand.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/rawnand.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/nand_ecc.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/sys_proto.h>
20 
21 /* The NAND flash driver defines */
22 #define ZYNQ_NAND_CMD_PHASE		1
23 #define ZYNQ_NAND_DATA_PHASE		2
24 #define ZYNQ_NAND_ECC_SIZE		512
25 #define ZYNQ_NAND_SET_OPMODE_8BIT	(0 << 0)
26 #define ZYNQ_NAND_SET_OPMODE_16BIT	(1 << 0)
27 #define ZYNQ_NAND_ECC_STATUS		(1 << 6)
28 #define ZYNQ_MEMC_CLRCR_INT_CLR1	(1 << 4)
29 #define ZYNQ_MEMC_SR_RAW_INT_ST1	(1 << 6)
30 #define ZYNQ_MEMC_SR_INT_ST1		(1 << 4)
31 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK	0xC
32 
33 /* Flash memory controller operating parameters */
34 #define ZYNQ_NAND_CLR_CONFIG	((0x1 << 1)  |	/* Disable interrupt */ \
35 				(0x1 << 4)   |	/* Clear interrupt */ \
36 				(0x1 << 6))	/* Disable ECC interrupt */
37 
38 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
39 
40 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
41 #define ZYNQ_NAND_SET_CYCLES	((0x2 << 20) |	/* t_rr from nand_cycles */ \
42 				(0x2 << 17)  |	/* t_ar from nand_cycles */ \
43 				(0x1 << 14)  |	/* t_clr from nand_cycles */ \
44 				(0x3 << 11)  |	/* t_wp from nand_cycles */ \
45 				(0x2 << 8)   |	/* t_rea from nand_cycles */ \
46 				(0x5 << 4)   |	/* t_wc from nand_cycles */ \
47 				(0x5 << 0))	/* t_rc from nand_cycles */
48 #endif
49 
50 
51 #define ZYNQ_NAND_DIRECT_CMD	((0x4 << 23) |	/* Chip 0 from interface 1 */ \
52 				(0x2 << 21))	/* UpdateRegs operation */
53 
54 #define ZYNQ_NAND_ECC_CONFIG	((0x1 << 2)  |	/* ECC available on APB */ \
55 				(0x1 << 4)   |	/* ECC read at end of page */ \
56 				(0x0 << 5))	/* No Jumping */
57 
58 #define ZYNQ_NAND_ECC_CMD1	((0x80)      |	/* Write command */ \
59 				(0x00 << 8)  |	/* Read command */ \
60 				(0x30 << 16) |	/* Read End command */ \
61 				(0x1 << 24))	/* Read End command calid */
62 
63 #define ZYNQ_NAND_ECC_CMD2	((0x85)      |	/* Write col change cmd */ \
64 				(0x05 << 8)  |	/* Read col change cmd */ \
65 				(0xE0 << 16) |	/* Read col change end cmd */ \
66 				(0x1 << 24))	/* Read col change
67 							end cmd valid */
68 /* AXI Address definitions */
69 #define START_CMD_SHIFT			3
70 #define END_CMD_SHIFT			11
71 #define END_CMD_VALID_SHIFT		20
72 #define ADDR_CYCLES_SHIFT		21
73 #define CLEAR_CS_SHIFT			21
74 #define ECC_LAST_SHIFT			10
75 #define COMMAND_PHASE			(0 << 19)
76 #define DATA_PHASE			(1 << 19)
77 #define ONDIE_ECC_FEATURE_ADDR		0x90
78 #define ONDIE_ECC_FEATURE_ENABLE	0x08
79 
80 #define ZYNQ_NAND_ECC_LAST	(1 << ECC_LAST_SHIFT)	/* Set ECC_Last */
81 #define ZYNQ_NAND_CLEAR_CS	(1 << CLEAR_CS_SHIFT)	/* Clear chip select */
82 
83 /* ECC block registers bit position and bit mask */
84 #define ZYNQ_NAND_ECC_BUSY	(1 << 6)	/* ECC block is busy */
85 #define ZYNQ_NAND_ECC_MASK	0x00FFFFFF	/* ECC value mask */
86 
87 #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK	0x0F
88 #define ZYNQ_NAND_COL_ADDR_CYCL_MASK	0xF0
89 
90 #define ZYNQ_NAND_MIO_NUM_NAND_8BIT	13
91 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT	8
92 
93 enum zynq_nand_bus_width {
94 	NAND_BW_UNKNOWN = -1,
95 	NAND_BW_8BIT,
96 	NAND_BW_16BIT,
97 };
98 
99 #ifndef NAND_CMD_LOCK_TIGHT
100 #define NAND_CMD_LOCK_TIGHT 0x2c
101 #endif
102 
103 #ifndef NAND_CMD_LOCK_STATUS
104 #define NAND_CMD_LOCK_STATUS 0x7a
105 #endif
106 
107 /* SMC register set */
108 struct zynq_nand_smc_regs {
109 	u32 csr;		/* 0x00 */
110 	u32 reserved0[2];
111 	u32 cfr;		/* 0x0C */
112 	u32 dcr;		/* 0x10 */
113 	u32 scr;		/* 0x14 */
114 	u32 sor;		/* 0x18 */
115 	u32 reserved1[249];
116 	u32 esr;		/* 0x400 */
117 	u32 emcr;		/* 0x404 */
118 	u32 emcmd1r;		/* 0x408 */
119 	u32 emcmd2r;		/* 0x40C */
120 	u32 reserved2[2];
121 	u32 eval0r;		/* 0x418 */
122 };
123 #define zynq_nand_smc_base	((struct zynq_nand_smc_regs __iomem *)\
124 				ZYNQ_SMC_BASEADDR)
125 
126 /*
127  * struct zynq_nand_info - Defines the NAND flash driver instance
128  * @parts:		Pointer to the mtd_partition structure
129  * @nand_base:		Virtual address of the NAND flash device
130  * @end_cmd_pending:	End command is pending
131  * @end_cmd:		End command
132  */
133 struct zynq_nand_info {
134 	void __iomem	*nand_base;
135 	u8		end_cmd_pending;
136 	u8		end_cmd;
137 };
138 
139 /*
140  * struct zynq_nand_command_format - Defines NAND flash command format
141  * @start_cmd:		First cycle command (Start command)
142  * @end_cmd:		Second cycle command (Last command)
143  * @addr_cycles:	Number of address cycles required to send the address
144  * @end_cmd_valid:	The second cycle command is valid for cmd or data phase
145  */
146 struct zynq_nand_command_format {
147 	u8 start_cmd;
148 	u8 end_cmd;
149 	u8 addr_cycles;
150 	u8 end_cmd_valid;
151 };
152 
153 /*  The NAND flash operations command format */
154 static const struct zynq_nand_command_format zynq_nand_commands[] = {
155 	{NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
156 	{NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
157 	{NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
158 	{NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
159 	{NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
160 	{NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
161 	{NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
162 	{NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
163 	{NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
164 	{NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
165 	{NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
166 	{NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
167 	{NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
168 	{NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
169 	{NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
170 	{NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
171 	{NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
172 	/* Add all the flash commands supported by the flash device */
173 };
174 
175 /* Define default oob placement schemes for large and small page devices */
176 static struct nand_ecclayout nand_oob_16 = {
177 	.eccbytes = 3,
178 	.eccpos = {0, 1, 2},
179 	.oobfree = {
180 		{ .offset = 8, .length = 8 }
181 	}
182 };
183 
184 static struct nand_ecclayout nand_oob_64 = {
185 	.eccbytes = 12,
186 	.eccpos = {
187 		   52, 53, 54, 55, 56, 57,
188 		   58, 59, 60, 61, 62, 63},
189 	.oobfree = {
190 		{ .offset = 2, .length = 50 }
191 	}
192 };
193 
194 static struct nand_ecclayout ondie_nand_oob_64 = {
195 	.eccbytes = 32,
196 
197 	.eccpos = {
198 		8, 9, 10, 11, 12, 13, 14, 15,
199 		24, 25, 26, 27, 28, 29, 30, 31,
200 		40, 41, 42, 43, 44, 45, 46, 47,
201 		56, 57, 58, 59, 60, 61, 62, 63
202 	},
203 
204 	.oobfree = {
205 		{ .offset = 4, .length = 4 },
206 		{ .offset = 20, .length = 4 },
207 		{ .offset = 36, .length = 4 },
208 		{ .offset = 52, .length = 4 }
209 	}
210 };
211 
212 /* bbt decriptors for chips with on-die ECC and
213    chips with 64-byte OOB */
214 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
215 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
216 
217 static struct nand_bbt_descr bbt_main_descr = {
218 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
219 		NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
220 	.offs = 4,
221 	.len = 4,
222 	.veroffs = 20,
223 	.maxblocks = 4,
224 	.pattern = bbt_pattern
225 };
226 
227 static struct nand_bbt_descr bbt_mirror_descr = {
228 	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
229 		NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
230 	.offs = 4,
231 	.len = 4,
232 	.veroffs = 20,
233 	.maxblocks = 4,
234 	.pattern = mirror_pattern
235 };
236 
237 /*
238  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
239  *
240  * returns: status for command completion, -1 for Timeout
241  */
zynq_nand_waitfor_ecc_completion(void)242 static int zynq_nand_waitfor_ecc_completion(void)
243 {
244 	unsigned long timeout;
245 	u32 status;
246 
247 	/* Wait max 10us */
248 	timeout = 10;
249 	status = readl(&zynq_nand_smc_base->esr);
250 	while (status & ZYNQ_NAND_ECC_BUSY) {
251 		status = readl(&zynq_nand_smc_base->esr);
252 		if (timeout == 0)
253 			return -1;
254 		timeout--;
255 		udelay(1);
256 	}
257 
258 	return status;
259 }
260 
261 /*
262  * zynq_nand_init_nand_flash - Initialize NAND controller
263  * @option:	Device property flags
264  *
265  * This function initializes the NAND flash interface on the NAND controller.
266  *
267  * returns:	0 on success or error value on failure
268  */
zynq_nand_init_nand_flash(int option)269 static int zynq_nand_init_nand_flash(int option)
270 {
271 	u32 status;
272 
273 	/* disable interrupts */
274 	writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
275 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
276 	/* Initialize the NAND interface by setting cycles and operation mode */
277 	writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
278 #endif
279 	if (option & NAND_BUSWIDTH_16)
280 		writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
281 	else
282 		writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
283 
284 	writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
285 
286 	/* Wait till the ECC operation is complete */
287 	status = zynq_nand_waitfor_ecc_completion();
288 	if (status < 0) {
289 		printf("%s: Timeout\n", __func__);
290 		return status;
291 	}
292 
293 	/* Set the command1 and command2 register */
294 	writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
295 	writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
296 
297 	return 0;
298 }
299 
300 /*
301  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
302  * @mtd:	Pointer to the mtd_info structure
303  * @data:	Pointer to the page data
304  * @ecc_code:	Pointer to the ECC buffer where ECC data needs to be stored
305  *
306  * This function retrieves the Hardware ECC data from the controller and returns
307  * ECC data back to the MTD subsystem.
308  *
309  * returns:	0 on success or error value on failure
310  */
zynq_nand_calculate_hwecc(struct mtd_info * mtd,const u8 * data,u8 * ecc_code)311 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
312 		u8 *ecc_code)
313 {
314 	u32 ecc_value = 0;
315 	u8 ecc_reg, ecc_byte;
316 	u32 ecc_status;
317 
318 	/* Wait till the ECC operation is complete */
319 	ecc_status = zynq_nand_waitfor_ecc_completion();
320 	if (ecc_status < 0) {
321 		printf("%s: Timeout\n", __func__);
322 		return ecc_status;
323 	}
324 
325 	for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
326 		/* Read ECC value for each block */
327 		ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
328 
329 		/* Get the ecc status from ecc read value */
330 		ecc_status = (ecc_value >> 24) & 0xFF;
331 
332 		/* ECC value valid */
333 		if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
334 			for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
335 				/* Copy ECC bytes to MTD buffer */
336 				*ecc_code = ecc_value & 0xFF;
337 				ecc_value = ecc_value >> 8;
338 				ecc_code++;
339 			}
340 		} else {
341 			debug("%s: ecc status failed\n", __func__);
342 		}
343 	}
344 
345 	return 0;
346 }
347 
348 /*
349  * onehot - onehot function
350  * @value:	value to check for onehot
351  *
352  * This function checks whether a value is onehot or not.
353  * onehot is if and only if one bit is set.
354  *
355  * FIXME: Try to move this in common.h
356  */
onehot(unsigned short value)357 static bool onehot(unsigned short value)
358 {
359 	bool onehot;
360 
361 	onehot = value && !(value & (value - 1));
362 	return onehot;
363 }
364 
365 /*
366  * zynq_nand_correct_data - ECC correction function
367  * @mtd:	Pointer to the mtd_info structure
368  * @buf:	Pointer to the page data
369  * @read_ecc:	Pointer to the ECC value read from spare data area
370  * @calc_ecc:	Pointer to the calculated ECC value
371  *
372  * This function corrects the ECC single bit errors & detects 2-bit errors.
373  *
374  * returns:	0 if no ECC errors found
375  *		1 if single bit error found and corrected.
376  *		-1 if multiple ECC errors found.
377  */
zynq_nand_correct_data(struct mtd_info * mtd,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)378 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
379 			unsigned char *read_ecc, unsigned char *calc_ecc)
380 {
381 	unsigned char bit_addr;
382 	unsigned int byte_addr;
383 	unsigned short ecc_odd, ecc_even;
384 	unsigned short read_ecc_lower, read_ecc_upper;
385 	unsigned short calc_ecc_lower, calc_ecc_upper;
386 
387 	read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
388 	read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
389 
390 	calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
391 	calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
392 
393 	ecc_odd = read_ecc_lower ^ calc_ecc_lower;
394 	ecc_even = read_ecc_upper ^ calc_ecc_upper;
395 
396 	if ((ecc_odd == 0) && (ecc_even == 0))
397 		return 0;       /* no error */
398 
399 	if (ecc_odd == (~ecc_even & 0xfff)) {
400 		/* bits [11:3] of error code is byte offset */
401 		byte_addr = (ecc_odd >> 3) & 0x1ff;
402 		/* bits [2:0] of error code is bit offset */
403 		bit_addr = ecc_odd & 0x7;
404 		/* Toggling error bit */
405 		buf[byte_addr] ^= (1 << bit_addr);
406 		return 1;
407 	}
408 
409 	if (onehot(ecc_odd | ecc_even))
410 		return 1; /* one error in parity */
411 
412 	return -1; /* Uncorrectable error */
413 }
414 
415 /*
416  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
417  * @mtd:	mtd info structure
418  * @chip:	nand chip info structure
419  * @page:	page number to read
420  * @sndcmd:	flag whether to issue read command or not
421  */
zynq_nand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)422 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
423 			int page)
424 {
425 	unsigned long data_phase_addr = 0;
426 	int data_width = 4;
427 	u8 *p;
428 
429 	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
430 
431 	p = chip->oob_poi;
432 	chip->read_buf(mtd, p, (mtd->oobsize - data_width));
433 	p += mtd->oobsize - data_width;
434 
435 	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
436 	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
437 	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
438 	chip->read_buf(mtd, p, data_width);
439 
440 	return 0;
441 }
442 
443 /*
444  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
445  * @mtd:	mtd info structure
446  * @chip:	nand chip info structure
447  * @page:	page number to write
448  */
zynq_nand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)449 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
450 			     int page)
451 {
452 	int status = 0, data_width = 4;
453 	const u8 *buf = chip->oob_poi;
454 	unsigned long data_phase_addr = 0;
455 
456 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
457 
458 	chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
459 	buf += mtd->oobsize - data_width;
460 
461 	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
462 	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
463 	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
464 	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
465 	chip->write_buf(mtd, buf, data_width);
466 
467 	/* Send command to program the OOB data */
468 	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
469 	status = chip->waitfunc(mtd, chip);
470 
471 	return status & NAND_STATUS_FAIL ? -EIO : 0;
472 }
473 
474 /*
475  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
476  * @mtd:        mtd info structure
477  * @chip:       nand chip info structure
478  * @buf:        buffer to store read data
479  * @oob_required: must write chip->oob_poi to OOB
480  * @page:       page number to read
481  */
zynq_nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)482 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
483 				   u8 *buf,  int oob_required, int page)
484 {
485 	unsigned long data_width = 4;
486 	unsigned long data_phase_addr = 0;
487 	u8 *p;
488 
489 	chip->read_buf(mtd, buf, mtd->writesize);
490 
491 	p = chip->oob_poi;
492 	chip->read_buf(mtd, p, (mtd->oobsize - data_width));
493 	p += (mtd->oobsize - data_width);
494 
495 	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
496 	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
497 	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
498 
499 	chip->read_buf(mtd, p, data_width);
500 	return 0;
501 }
502 
zynq_nand_read_page_raw_nooob(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)503 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
504 		struct nand_chip *chip, u8 *buf, int oob_required, int page)
505 {
506 	chip->read_buf(mtd, buf, mtd->writesize);
507 	return 0;
508 }
509 
zynq_nand_read_subpage_raw(struct mtd_info * mtd,struct nand_chip * chip,u32 data_offs,u32 readlen,u8 * buf,int page)510 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
511 				    struct nand_chip *chip, u32 data_offs,
512 				    u32 readlen, u8 *buf, int page)
513 {
514 	if (data_offs != 0) {
515 		chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
516 		buf += data_offs;
517 	}
518 	chip->read_buf(mtd, buf, readlen);
519 
520 	return 0;
521 }
522 
523 /*
524  * zynq_nand_write_page_raw - [Intern] raw page write function
525  * @mtd:        mtd info structure
526  * @chip:       nand chip info structure
527  * @buf:        data buffer
528  * @oob_required: must write chip->oob_poi to OOB
529  */
zynq_nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const u8 * buf,int oob_required,int page)530 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
531 	struct nand_chip *chip, const u8 *buf, int oob_required, int page)
532 {
533 	unsigned long data_width = 4;
534 	unsigned long data_phase_addr = 0;
535 	u8 *p;
536 
537 	chip->write_buf(mtd, buf, mtd->writesize);
538 
539 	p = chip->oob_poi;
540 	chip->write_buf(mtd, p, (mtd->oobsize - data_width));
541 	p += (mtd->oobsize - data_width);
542 
543 	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
544 	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
545 	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
546 	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
547 
548 	chip->write_buf(mtd, p, data_width);
549 
550 	return 0;
551 }
552 
553 /*
554  * nand_write_page_hwecc - Hardware ECC based page write function
555  * @mtd:	Pointer to the mtd info structure
556  * @chip:	Pointer to the NAND chip info structure
557  * @buf:	Pointer to the data buffer
558  * @oob_required: must write chip->oob_poi to OOB
559  *
560  * This functions writes data and hardware generated ECC values in to the page.
561  */
zynq_nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const u8 * buf,int oob_required,int page)562 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
563 	struct nand_chip *chip, const u8 *buf, int oob_required, int page)
564 {
565 	int i, eccsteps, eccsize = chip->ecc.size;
566 	u8 *ecc_calc = chip->buffers->ecccalc;
567 	const u8 *p = buf;
568 	u32 *eccpos = chip->ecc.layout->eccpos;
569 	unsigned long data_phase_addr = 0;
570 	unsigned long data_width = 4;
571 	u8 *oob_ptr;
572 
573 	for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
574 		chip->write_buf(mtd, p, eccsize);
575 		p += eccsize;
576 	}
577 	chip->write_buf(mtd, p, (eccsize - data_width));
578 	p += eccsize - data_width;
579 
580 	/* Set ECC Last bit to 1 */
581 	data_phase_addr = (unsigned long) chip->IO_ADDR_W;
582 	data_phase_addr |= ZYNQ_NAND_ECC_LAST;
583 	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
584 	chip->write_buf(mtd, p, data_width);
585 
586 	/* Wait for ECC to be calculated and read the error values */
587 	p = buf;
588 	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
589 
590 	for (i = 0; i < chip->ecc.total; i++)
591 		chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
592 
593 	/* Clear ECC last bit */
594 	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
595 	data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
596 	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
597 
598 	/* Write the spare area with ECC bytes */
599 	oob_ptr = chip->oob_poi;
600 	chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
601 
602 	data_phase_addr = (unsigned long)chip->IO_ADDR_W;
603 	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
604 	data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
605 	chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
606 	oob_ptr += (mtd->oobsize - data_width);
607 	chip->write_buf(mtd, oob_ptr, data_width);
608 
609 	return 0;
610 }
611 
612 /*
613  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
614  * write function
615  * @mtd:	mtd info structure
616  * @chip:	nand chip info structure
617  * @buf:	data buffer
618  * @oob_required: must write chip->oob_poi to OOB
619  */
zynq_nand_write_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,const u8 * buf,int oob_required,int page)620 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
621 	struct nand_chip *chip, const u8 *buf, int oob_required, int page)
622 {
623 	int i, eccsize = chip->ecc.size;
624 	int eccbytes = chip->ecc.bytes;
625 	int eccsteps = chip->ecc.steps;
626 	u8 *ecc_calc = chip->buffers->ecccalc;
627 	const u8 *p = buf;
628 	u32 *eccpos = chip->ecc.layout->eccpos;
629 
630 	/* Software ecc calculation */
631 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
632 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
633 
634 	for (i = 0; i < chip->ecc.total; i++)
635 		chip->oob_poi[eccpos[i]] = ecc_calc[i];
636 
637 	return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
638 }
639 
640 /*
641  * nand_read_page_hwecc - Hardware ECC based page read function
642  * @mtd:	Pointer to the mtd info structure
643  * @chip:	Pointer to the NAND chip info structure
644  * @buf:	Pointer to the buffer to store read data
645  * @oob_required: must write chip->oob_poi to OOB
646  * @page:	page number to read
647  *
648  * This functions reads data and checks the data integrity by comparing hardware
649  * generated ECC values and read ECC values from spare area.
650  *
651  * returns:	0 always and updates ECC operation status in to MTD structure
652  */
zynq_nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)653 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
654 	struct nand_chip *chip, u8 *buf, int oob_required, int page)
655 {
656 	int i, stat, eccsteps, eccsize = chip->ecc.size;
657 	int eccbytes = chip->ecc.bytes;
658 	u8 *p = buf;
659 	u8 *ecc_calc = chip->buffers->ecccalc;
660 	u8 *ecc_code = chip->buffers->ecccode;
661 	u32 *eccpos = chip->ecc.layout->eccpos;
662 	unsigned long data_phase_addr = 0;
663 	unsigned long data_width = 4;
664 	u8 *oob_ptr;
665 
666 	for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
667 		chip->read_buf(mtd, p, eccsize);
668 		p += eccsize;
669 	}
670 	chip->read_buf(mtd, p, (eccsize - data_width));
671 	p += eccsize - data_width;
672 
673 	/* Set ECC Last bit to 1 */
674 	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
675 	data_phase_addr |= ZYNQ_NAND_ECC_LAST;
676 	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
677 	chip->read_buf(mtd, p, data_width);
678 
679 	/* Read the calculated ECC value */
680 	p = buf;
681 	chip->ecc.calculate(mtd, p, &ecc_calc[0]);
682 
683 	/* Clear ECC last bit */
684 	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
685 	data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
686 	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
687 
688 	/* Read the stored ECC value */
689 	oob_ptr = chip->oob_poi;
690 	chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
691 
692 	/* de-assert chip select */
693 	data_phase_addr = (unsigned long)chip->IO_ADDR_R;
694 	data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
695 	chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
696 
697 	oob_ptr += (mtd->oobsize - data_width);
698 	chip->read_buf(mtd, oob_ptr, data_width);
699 
700 	for (i = 0; i < chip->ecc.total; i++)
701 		ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
702 
703 	eccsteps = chip->ecc.steps;
704 	p = buf;
705 
706 	/* Check ECC error for all blocks and correct if it is correctable */
707 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
708 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
709 		if (stat < 0)
710 			mtd->ecc_stats.failed++;
711 		else
712 			mtd->ecc_stats.corrected += stat;
713 	}
714 	return 0;
715 }
716 
717 /*
718  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
719  * read function
720  * @mtd:	mtd info structure
721  * @chip:	nand chip info structure
722  * @buf:	buffer to store read data
723  * @page:	page number to read
724  */
zynq_nand_read_page_swecc(struct mtd_info * mtd,struct nand_chip * chip,u8 * buf,int oob_required,int page)725 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
726 	struct nand_chip *chip, u8 *buf, int oob_required,  int page)
727 {
728 	int i, eccsize = chip->ecc.size;
729 	int eccbytes = chip->ecc.bytes;
730 	int eccsteps = chip->ecc.steps;
731 	u8 *p = buf;
732 	u8 *ecc_calc = chip->buffers->ecccalc;
733 	u8 *ecc_code = chip->buffers->ecccode;
734 	u32 *eccpos = chip->ecc.layout->eccpos;
735 
736 	chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
737 
738 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
739 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
740 
741 	for (i = 0; i < chip->ecc.total; i++)
742 		ecc_code[i] = chip->oob_poi[eccpos[i]];
743 
744 	eccsteps = chip->ecc.steps;
745 	p = buf;
746 
747 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
748 		int stat;
749 
750 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
751 		if (stat < 0)
752 			mtd->ecc_stats.failed++;
753 		else
754 			mtd->ecc_stats.corrected += stat;
755 	}
756 	return 0;
757 }
758 
759 /*
760  * zynq_nand_select_chip - Select the flash device
761  * @mtd:	Pointer to the mtd_info structure
762  * @chip:	Chip number to be selected
763  *
764  * This function is empty as the NAND controller handles chip select line
765  * internally based on the chip address passed in command and data phase.
766  */
zynq_nand_select_chip(struct mtd_info * mtd,int chip)767 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
768 {
769 	/* Not support multiple chips yet */
770 }
771 
772 /*
773  * zynq_nand_cmd_function - Send command to NAND device
774  * @mtd:	Pointer to the mtd_info structure
775  * @command:	The command to be sent to the flash device
776  * @column:	The column address for this command, -1 if none
777  * @page_addr:	The page address for this command, -1 if none
778  */
zynq_nand_cmd_function(struct mtd_info * mtd,unsigned int command,int column,int page_addr)779 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
780 				 int column, int page_addr)
781 {
782 	struct nand_chip *chip = mtd->priv;
783 	const struct zynq_nand_command_format *curr_cmd = NULL;
784 	u8 addr_cycles = 0;
785 	struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
786 	void *cmd_addr;
787 	unsigned long cmd_data = 0;
788 	unsigned long cmd_phase_addr = 0;
789 	unsigned long data_phase_addr = 0;
790 	u8 end_cmd = 0;
791 	u8 end_cmd_valid = 0;
792 	u32 index;
793 
794 	if (xnand->end_cmd_pending) {
795 		/* Check for end command if this command request is same as the
796 		 * pending command then return
797 		 */
798 		if (xnand->end_cmd == command) {
799 			xnand->end_cmd = 0;
800 			xnand->end_cmd_pending = 0;
801 			return;
802 		}
803 	}
804 
805 	/* Emulate NAND_CMD_READOOB for large page device */
806 	if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
807 	    (command == NAND_CMD_READOOB)) {
808 		column += mtd->writesize;
809 		command = NAND_CMD_READ0;
810 	}
811 
812 	/* Get the command format */
813 	for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
814 		if (command == zynq_nand_commands[index].start_cmd)
815 			break;
816 
817 	if (index == ARRAY_SIZE(zynq_nand_commands)) {
818 		printf("%s: Unsupported start cmd %02x\n", __func__, command);
819 		return;
820 	}
821 	curr_cmd = &zynq_nand_commands[index];
822 
823 	/* Clear interrupt */
824 	writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
825 
826 	/* Get the command phase address */
827 	if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
828 		end_cmd_valid = 1;
829 
830 	if (curr_cmd->end_cmd == NAND_CMD_NONE)
831 		end_cmd = 0x0;
832 	else
833 		end_cmd = curr_cmd->end_cmd;
834 
835 	if (command == NAND_CMD_READ0 ||
836 	    command == NAND_CMD_SEQIN) {
837 		addr_cycles = chip->onfi_params.addr_cycles &
838 				ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
839 		addr_cycles += ((chip->onfi_params.addr_cycles &
840 				ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
841 	} else {
842 		addr_cycles = curr_cmd->addr_cycles;
843 	}
844 
845 	cmd_phase_addr = (unsigned long)xnand->nand_base	|
846 			(addr_cycles << ADDR_CYCLES_SHIFT)	|
847 			(end_cmd_valid << END_CMD_VALID_SHIFT)		|
848 			(COMMAND_PHASE)					|
849 			(end_cmd << END_CMD_SHIFT)			|
850 			(curr_cmd->start_cmd << START_CMD_SHIFT);
851 
852 	cmd_addr = (void __iomem *)cmd_phase_addr;
853 
854 	/* Get the data phase address */
855 	end_cmd_valid = 0;
856 
857 	data_phase_addr = (unsigned long)xnand->nand_base	|
858 			(0x0 << CLEAR_CS_SHIFT)				|
859 			(end_cmd_valid << END_CMD_VALID_SHIFT)		|
860 			(DATA_PHASE)					|
861 			(end_cmd << END_CMD_SHIFT)			|
862 			(0x0 << ECC_LAST_SHIFT);
863 
864 	chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
865 	chip->IO_ADDR_W = chip->IO_ADDR_R;
866 
867 	/* Command phase AXI Read & Write */
868 	if (column != -1 && page_addr != -1) {
869 		/* Adjust columns for 16 bit bus width */
870 		if (chip->options & NAND_BUSWIDTH_16)
871 			column >>= 1;
872 		cmd_data = column;
873 		if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
874 			cmd_data |= page_addr << 16;
875 			/* Another address cycle for devices > 128MiB */
876 			if (chip->chipsize > (128 << 20)) {
877 				writel(cmd_data, cmd_addr);
878 				cmd_data = (page_addr >> 16);
879 			}
880 		} else {
881 			cmd_data |= page_addr << 8;
882 		}
883 	} else if (page_addr != -1)  { /* Erase */
884 		cmd_data = page_addr;
885 	} else if (column != -1) { /* Change read/write column, read id etc */
886 		/* Adjust columns for 16 bit bus width */
887 		if ((chip->options & NAND_BUSWIDTH_16) &&
888 		    ((command == NAND_CMD_READ0) ||
889 		     (command == NAND_CMD_SEQIN) ||
890 		     (command == NAND_CMD_RNDOUT) ||
891 		     (command == NAND_CMD_RNDIN)))
892 			column >>= 1;
893 		cmd_data = column;
894 	}
895 
896 	writel(cmd_data, cmd_addr);
897 
898 	if (curr_cmd->end_cmd_valid) {
899 		xnand->end_cmd = curr_cmd->end_cmd;
900 		xnand->end_cmd_pending = 1;
901 	}
902 
903 	ndelay(100);
904 
905 	if ((command == NAND_CMD_READ0) ||
906 	    (command == NAND_CMD_RESET) ||
907 	    (command == NAND_CMD_PARAM) ||
908 	    (command == NAND_CMD_GET_FEATURES))
909 		/* wait until command is processed */
910 		nand_wait_ready(mtd);
911 }
912 
913 /*
914  * zynq_nand_read_buf - read chip data into buffer
915  * @mtd:        MTD device structure
916  * @buf:        buffer to store date
917  * @len:        number of bytes to read
918  */
zynq_nand_read_buf(struct mtd_info * mtd,u8 * buf,int len)919 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
920 {
921 	struct nand_chip *chip = mtd->priv;
922 
923 	/* Make sure that buf is 32 bit aligned */
924 	if (((unsigned long)buf & 0x3) != 0) {
925 		if (((unsigned long)buf & 0x1) != 0) {
926 			if (len) {
927 				*buf = readb(chip->IO_ADDR_R);
928 				buf += 1;
929 				len--;
930 			}
931 		}
932 
933 		if (((unsigned long)buf & 0x3) != 0) {
934 			if (len >= 2) {
935 				*(u16 *)buf = readw(chip->IO_ADDR_R);
936 				buf += 2;
937 				len -= 2;
938 			}
939 		}
940 	}
941 
942 	/* copy aligned data */
943 	while (len >= 4) {
944 		*(u32 *)buf = readl(chip->IO_ADDR_R);
945 		buf += 4;
946 		len -= 4;
947 	}
948 
949 	/* mop up any remaining bytes */
950 	if (len) {
951 		if (len >= 2) {
952 			*(u16 *)buf = readw(chip->IO_ADDR_R);
953 			buf += 2;
954 			len -= 2;
955 		}
956 		if (len)
957 			*buf = readb(chip->IO_ADDR_R);
958 	}
959 }
960 
961 /*
962  * zynq_nand_write_buf - write buffer to chip
963  * @mtd:        MTD device structure
964  * @buf:        data buffer
965  * @len:        number of bytes to write
966  */
zynq_nand_write_buf(struct mtd_info * mtd,const u8 * buf,int len)967 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
968 {
969 	struct nand_chip *chip = mtd->priv;
970 	const u32 *nand = chip->IO_ADDR_W;
971 
972 	/* Make sure that buf is 32 bit aligned */
973 	if (((unsigned long)buf & 0x3) != 0) {
974 		if (((unsigned long)buf & 0x1) != 0) {
975 			if (len) {
976 				writeb(*buf, nand);
977 				buf += 1;
978 				len--;
979 			}
980 		}
981 
982 		if (((unsigned long)buf & 0x3) != 0) {
983 			if (len >= 2) {
984 				writew(*(u16 *)buf, nand);
985 				buf += 2;
986 				len -= 2;
987 			}
988 		}
989 	}
990 
991 	/* copy aligned data */
992 	while (len >= 4) {
993 		writel(*(u32 *)buf, nand);
994 		buf += 4;
995 		len -= 4;
996 	}
997 
998 	/* mop up any remaining bytes */
999 	if (len) {
1000 		if (len >= 2) {
1001 			writew(*(u16 *)buf, nand);
1002 			buf += 2;
1003 			len -= 2;
1004 		}
1005 
1006 		if (len)
1007 			writeb(*buf, nand);
1008 	}
1009 }
1010 
1011 /*
1012  * zynq_nand_device_ready - Check device ready/busy line
1013  * @mtd:	Pointer to the mtd_info structure
1014  *
1015  * returns:	0 on busy or 1 on ready state
1016  */
zynq_nand_device_ready(struct mtd_info * mtd)1017 static int zynq_nand_device_ready(struct mtd_info *mtd)
1018 {
1019 	u32 csr_val;
1020 
1021 	csr_val = readl(&zynq_nand_smc_base->csr);
1022 	/* Check the raw_int_status1 bit */
1023 	if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
1024 		/* Clear the interrupt condition */
1025 		writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
1026 		return 1;
1027 	}
1028 
1029 	return 0;
1030 }
1031 
zynq_nand_check_is_16bit_bw_flash(void)1032 static int zynq_nand_check_is_16bit_bw_flash(void)
1033 {
1034 	int is_16bit_bw = NAND_BW_UNKNOWN;
1035 	int mio_num_8bit = 0, mio_num_16bit = 0;
1036 
1037 	mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
1038 	if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
1039 		is_16bit_bw = NAND_BW_8BIT;
1040 
1041 	mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
1042 	if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
1043 	    mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
1044 		is_16bit_bw = NAND_BW_16BIT;
1045 
1046 	return is_16bit_bw;
1047 }
1048 
zynq_nand_init(struct nand_chip * nand_chip,int devnum)1049 static int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
1050 {
1051 	struct zynq_nand_info *xnand;
1052 	struct mtd_info *mtd;
1053 	unsigned long ecc_page_size;
1054 	u8 maf_id, dev_id, i;
1055 	u8 get_feature[4];
1056 	u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1057 	unsigned long ecc_cfg;
1058 	int ondie_ecc_enabled = 0;
1059 	int err = -1;
1060 	int is_16bit_bw;
1061 
1062 	xnand = calloc(1, sizeof(struct zynq_nand_info));
1063 	if (!xnand) {
1064 		printf("%s: failed to allocate\n", __func__);
1065 		goto fail;
1066 	}
1067 
1068 	xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1069 	mtd = nand_to_mtd(nand_chip);
1070 
1071 	nand_chip->priv = xnand;
1072 	mtd->priv = nand_chip;
1073 
1074 	/* Set address of NAND IO lines */
1075 	nand_chip->IO_ADDR_R = xnand->nand_base;
1076 	nand_chip->IO_ADDR_W = xnand->nand_base;
1077 
1078 	/* Set the driver entry points for MTD */
1079 	nand_chip->cmdfunc = zynq_nand_cmd_function;
1080 	nand_chip->dev_ready = zynq_nand_device_ready;
1081 	nand_chip->select_chip = zynq_nand_select_chip;
1082 
1083 	/* If we don't set this delay driver sets 20us by default */
1084 	nand_chip->chip_delay = 30;
1085 
1086 	/* Buffer read/write routines */
1087 	nand_chip->read_buf = zynq_nand_read_buf;
1088 	nand_chip->write_buf = zynq_nand_write_buf;
1089 
1090 	is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
1091 	if (is_16bit_bw == NAND_BW_UNKNOWN) {
1092 		printf("%s: Unable detect NAND based on MIO settings\n",
1093 		       __func__);
1094 		goto fail;
1095 	}
1096 
1097 	if (is_16bit_bw == NAND_BW_16BIT)
1098 		nand_chip->options = NAND_BUSWIDTH_16;
1099 
1100 	nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1101 
1102 	/* Initialize the NAND flash interface on NAND controller */
1103 	if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1104 		printf("%s: nand flash init failed\n", __func__);
1105 		goto fail;
1106 	}
1107 
1108 	/* first scan to find the device and get the page size */
1109 	if (nand_scan_ident(mtd, 1, NULL)) {
1110 		printf("%s: nand_scan_ident failed\n", __func__);
1111 		goto fail;
1112 	}
1113 	/* Send the command for reading device ID */
1114 	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1115 	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1116 
1117 	/* Read manufacturer and device IDs */
1118 	maf_id = nand_chip->read_byte(mtd);
1119 	dev_id = nand_chip->read_byte(mtd);
1120 
1121 	if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1122 				 (dev_id == 0xa1) || (dev_id == 0xb1) ||
1123 				 (dev_id == 0xaa) || (dev_id == 0xba) ||
1124 				 (dev_id == 0xda) || (dev_id == 0xca) ||
1125 				 (dev_id == 0xac) || (dev_id == 0xbc) ||
1126 				 (dev_id == 0xdc) || (dev_id == 0xcc) ||
1127 				 (dev_id == 0xa3) || (dev_id == 0xb3) ||
1128 				 (dev_id == 0xd3) || (dev_id == 0xc3))) {
1129 		nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1130 						ONDIE_ECC_FEATURE_ADDR, -1);
1131 		for (i = 0; i < 4; i++)
1132 			writeb(set_feature[i], nand_chip->IO_ADDR_W);
1133 
1134 		/* Wait for 1us after writing data with SET_FEATURES command */
1135 		ndelay(1000);
1136 
1137 		nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1138 						ONDIE_ECC_FEATURE_ADDR, -1);
1139 		nand_chip->read_buf(mtd, get_feature, 4);
1140 
1141 		if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1142 			debug("%s: OnDie ECC flash\n", __func__);
1143 			ondie_ecc_enabled = 1;
1144 		} else {
1145 			printf("%s: Unable to detect OnDie ECC\n", __func__);
1146 		}
1147 	}
1148 
1149 	if (ondie_ecc_enabled) {
1150 		/* Bypass the controller ECC block */
1151 		ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1152 		ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1153 		writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1154 
1155 		/* The software ECC routines won't work
1156 		 * with the SMC controller
1157 		 */
1158 		nand_chip->ecc.mode = NAND_ECC_HW;
1159 		nand_chip->ecc.strength = 1;
1160 		nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1161 		nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1162 		nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1163 		nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1164 		nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1165 		nand_chip->ecc.read_oob = zynq_nand_read_oob;
1166 		nand_chip->ecc.write_oob = zynq_nand_write_oob;
1167 		nand_chip->ecc.size = mtd->writesize;
1168 		nand_chip->ecc.bytes = 0;
1169 
1170 		/* NAND with on-die ECC supports subpage reads */
1171 		nand_chip->options |= NAND_SUBPAGE_READ;
1172 
1173 		/* On-Die ECC spare bytes offset 8 is used for ECC codes */
1174 		if (ondie_ecc_enabled) {
1175 			nand_chip->ecc.layout = &ondie_nand_oob_64;
1176 			/* Use the BBT pattern descriptors */
1177 			nand_chip->bbt_td = &bbt_main_descr;
1178 			nand_chip->bbt_md = &bbt_mirror_descr;
1179 		}
1180 	} else {
1181 		/* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1182 		nand_chip->ecc.mode = NAND_ECC_HW;
1183 		nand_chip->ecc.strength = 1;
1184 		nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1185 		nand_chip->ecc.bytes = 3;
1186 		nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1187 		nand_chip->ecc.correct = zynq_nand_correct_data;
1188 		nand_chip->ecc.hwctl = NULL;
1189 		nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1190 		nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1191 		nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1192 		nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1193 		nand_chip->ecc.read_oob = zynq_nand_read_oob;
1194 		nand_chip->ecc.write_oob = zynq_nand_write_oob;
1195 
1196 		switch (mtd->writesize) {
1197 		case 512:
1198 			ecc_page_size = 0x1;
1199 			/* Set the ECC memory config register */
1200 			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1201 			       &zynq_nand_smc_base->emcr);
1202 			break;
1203 		case 1024:
1204 			ecc_page_size = 0x2;
1205 			/* Set the ECC memory config register */
1206 			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1207 			       &zynq_nand_smc_base->emcr);
1208 			break;
1209 		case 2048:
1210 			ecc_page_size = 0x3;
1211 			/* Set the ECC memory config register */
1212 			writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1213 			       &zynq_nand_smc_base->emcr);
1214 			break;
1215 		default:
1216 			nand_chip->ecc.mode = NAND_ECC_SOFT;
1217 			nand_chip->ecc.calculate = nand_calculate_ecc;
1218 			nand_chip->ecc.correct = nand_correct_data;
1219 			nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1220 			nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1221 			nand_chip->ecc.size = 256;
1222 			break;
1223 		}
1224 
1225 		if (mtd->oobsize == 16)
1226 			nand_chip->ecc.layout = &nand_oob_16;
1227 		else if (mtd->oobsize == 64)
1228 			nand_chip->ecc.layout = &nand_oob_64;
1229 		else
1230 			printf("%s: No oob layout found\n", __func__);
1231 	}
1232 
1233 	/* Second phase scan */
1234 	if (nand_scan_tail(mtd)) {
1235 		printf("%s: nand_scan_tail failed\n", __func__);
1236 		goto fail;
1237 	}
1238 	if (nand_register(devnum, mtd))
1239 		goto fail;
1240 	return 0;
1241 fail:
1242 	free(xnand);
1243 	return err;
1244 }
1245 
1246 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1247 
board_nand_init(void)1248 void board_nand_init(void)
1249 {
1250 	struct nand_chip *nand = &nand_chip[0];
1251 
1252 	if (zynq_nand_init(nand, 0))
1253 		puts("ZYNQ NAND init failed\n");
1254 }
1255