xref: /openbmc/linux/drivers/media/platform/st/sti/bdisp/bdisp-reg.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Copyright (C) STMicroelectronics SA 2014
4   * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
5   */
6  
7  struct bdisp_node {
8  	/* 0 - General */
9  	u32 nip;
10  	u32 cic;
11  	u32 ins;
12  	u32 ack;
13  	/* 1 - Target */
14  	u32 tba;
15  	u32 tty;
16  	u32 txy;
17  	u32 tsz;
18  	/* 2 - Color Fill */
19  	u32 s1cf;
20  	u32 s2cf;
21  	/* 3 - Source 1 */
22  	u32 s1ba;
23  	u32 s1ty;
24  	u32 s1xy;
25  	u32 s1sz_tsz;
26  	/* 4 - Source 2 */
27  	u32 s2ba;
28  	u32 s2ty;
29  	u32 s2xy;
30  	u32 s2sz;
31  	/* 5 - Source 3 */
32  	u32 s3ba;
33  	u32 s3ty;
34  	u32 s3xy;
35  	u32 s3sz;
36  	/* 6 - Clipping */
37  	u32 cwo;
38  	u32 cws;
39  	/* 7 - CLUT */
40  	u32 cco;
41  	u32 cml;
42  	/* 8 - Filter & Mask */
43  	u32 fctl;
44  	u32 pmk;
45  	/* 9 - Chroma Filter */
46  	u32 rsf;
47  	u32 rzi;
48  	u32 hfp;
49  	u32 vfp;
50  	/* 10 - Luma Filter */
51  	u32 y_rsf;
52  	u32 y_rzi;
53  	u32 y_hfp;
54  	u32 y_vfp;
55  	/* 11 - Flicker */
56  	u32 ff0;
57  	u32 ff1;
58  	u32 ff2;
59  	u32 ff3;
60  	/* 12 - Color Key */
61  	u32 key1;
62  	u32 key2;
63  	/* 14 - Static Address & User */
64  	u32 sar;
65  	u32 usr;
66  	/* 15 - Input Versatile Matrix */
67  	u32 ivmx0;
68  	u32 ivmx1;
69  	u32 ivmx2;
70  	u32 ivmx3;
71  	/* 16 - Output Versatile Matrix */
72  	u32 ovmx0;
73  	u32 ovmx1;
74  	u32 ovmx2;
75  	u32 ovmx3;
76  	/* 17 - Pace */
77  	u32 pace;
78  	/* 18 - VC1R & DEI */
79  	u32 vc1r;
80  	u32 dei;
81  	/* 19 - Gradient Fill */
82  	u32 hgf;
83  	u32 vgf;
84  };
85  
86  /* HW registers : static */
87  #define BLT_CTL                 0x0A00
88  #define BLT_ITS                 0x0A04
89  #define BLT_STA1                0x0A08
90  #define BLT_AQ1_CTL             0x0A60
91  #define BLT_AQ1_IP              0x0A64
92  #define BLT_AQ1_LNA             0x0A68
93  #define BLT_AQ1_STA             0x0A6C
94  #define BLT_ITM0                0x0AD0
95  /* HW registers : plugs */
96  #define BLT_PLUGS1_OP2          0x0B04
97  #define BLT_PLUGS1_CHZ          0x0B08
98  #define BLT_PLUGS1_MSZ          0x0B0C
99  #define BLT_PLUGS1_PGZ          0x0B10
100  #define BLT_PLUGS2_OP2          0x0B24
101  #define BLT_PLUGS2_CHZ          0x0B28
102  #define BLT_PLUGS2_MSZ          0x0B2C
103  #define BLT_PLUGS2_PGZ          0x0B30
104  #define BLT_PLUGS3_OP2          0x0B44
105  #define BLT_PLUGS3_CHZ          0x0B48
106  #define BLT_PLUGS3_MSZ          0x0B4C
107  #define BLT_PLUGS3_PGZ          0x0B50
108  #define BLT_PLUGT_OP2           0x0B84
109  #define BLT_PLUGT_CHZ           0x0B88
110  #define BLT_PLUGT_MSZ           0x0B8C
111  #define BLT_PLUGT_PGZ           0x0B90
112  /* HW registers : node */
113  #define BLT_NIP                 0x0C00
114  #define BLT_CIC                 0x0C04
115  #define BLT_INS                 0x0C08
116  #define BLT_ACK                 0x0C0C
117  #define BLT_TBA                 0x0C10
118  #define BLT_TTY                 0x0C14
119  #define BLT_TXY                 0x0C18
120  #define BLT_TSZ                 0x0C1C
121  #define BLT_S1BA                0x0C28
122  #define BLT_S1TY                0x0C2C
123  #define BLT_S1XY                0x0C30
124  #define BLT_S2BA                0x0C38
125  #define BLT_S2TY                0x0C3C
126  #define BLT_S2XY                0x0C40
127  #define BLT_S2SZ                0x0C44
128  #define BLT_S3BA                0x0C48
129  #define BLT_S3TY                0x0C4C
130  #define BLT_S3XY                0x0C50
131  #define BLT_S3SZ                0x0C54
132  #define BLT_FCTL                0x0C68
133  #define BLT_RSF                 0x0C70
134  #define BLT_RZI                 0x0C74
135  #define BLT_HFP                 0x0C78
136  #define BLT_VFP                 0x0C7C
137  #define BLT_Y_RSF               0x0C80
138  #define BLT_Y_RZI               0x0C84
139  #define BLT_Y_HFP               0x0C88
140  #define BLT_Y_VFP               0x0C8C
141  #define BLT_IVMX0               0x0CC0
142  #define BLT_IVMX1               0x0CC4
143  #define BLT_IVMX2               0x0CC8
144  #define BLT_IVMX3               0x0CCC
145  #define BLT_OVMX0               0x0CD0
146  #define BLT_OVMX1               0x0CD4
147  #define BLT_OVMX2               0x0CD8
148  #define BLT_OVMX3               0x0CDC
149  #define BLT_DEI                 0x0CEC
150  /* HW registers : filters */
151  #define BLT_HFC_N               0x0D00
152  #define BLT_VFC_N               0x0D90
153  #define BLT_Y_HFC_N             0x0E00
154  #define BLT_Y_VFC_N             0x0E90
155  #define BLT_NB_H_COEF           16
156  #define BLT_NB_V_COEF           10
157  
158  /* Registers values */
159  #define BLT_CTL_RESET           BIT(31)         /* Global soft reset */
160  
161  #define BLT_ITS_AQ1_LNA         BIT(12)         /* AQ1 LNA reached */
162  
163  #define BLT_STA1_IDLE           BIT(0)          /* BDISP idle */
164  
165  #define BLT_AQ1_CTL_CFG         0x80400003      /* Enable, P3, LNA reached */
166  
167  #define BLT_INS_S1_MASK         (BIT(0) | BIT(1) | BIT(2))
168  #define BLT_INS_S1_OFF          0x00000000      /* src1 disabled */
169  #define BLT_INS_S1_MEM          0x00000001      /* src1 fetched from memory */
170  #define BLT_INS_S1_CF           0x00000003      /* src1 color fill */
171  #define BLT_INS_S1_COPY         0x00000004      /* src1 direct copy */
172  #define BLT_INS_S1_FILL         0x00000007      /* src1 firect fill */
173  #define BLT_INS_S2_MASK         (BIT(3) | BIT(4))
174  #define BLT_INS_S2_OFF          0x00000000      /* src2 disabled */
175  #define BLT_INS_S2_MEM          0x00000008      /* src2 fetched from memory */
176  #define BLT_INS_S2_CF           0x00000018      /* src2 color fill */
177  #define BLT_INS_S3_MASK         BIT(5)
178  #define BLT_INS_S3_OFF          0x00000000      /* src3 disabled */
179  #define BLT_INS_S3_MEM          0x00000020      /* src3 fetched from memory */
180  #define BLT_INS_IVMX            BIT(6)          /* Input versatile matrix */
181  #define BLT_INS_CLUT            BIT(7)          /* Color Look Up Table */
182  #define BLT_INS_SCALE           BIT(8)          /* Scaling */
183  #define BLT_INS_FLICK           BIT(9)          /* Flicker filter */
184  #define BLT_INS_CLIP            BIT(10)         /* Clipping */
185  #define BLT_INS_CKEY            BIT(11)         /* Color key */
186  #define BLT_INS_OVMX            BIT(12)         /* Output versatile matrix */
187  #define BLT_INS_DEI             BIT(13)         /* Deinterlace */
188  #define BLT_INS_PMASK           BIT(14)         /* Plane mask */
189  #define BLT_INS_VC1R            BIT(17)         /* VC1 Range mapping */
190  #define BLT_INS_ROTATE          BIT(18)         /* Rotation */
191  #define BLT_INS_GRAD            BIT(19)         /* Gradient fill */
192  #define BLT_INS_AQLOCK          BIT(29)         /* AQ lock */
193  #define BLT_INS_PACE            BIT(30)         /* Pace down */
194  #define BLT_INS_IRQ             BIT(31)         /* Raise IRQ when node done */
195  #define BLT_CIC_ALL_GRP         0x000FDFFC      /* all valid groups present */
196  #define BLT_ACK_BYPASS_S2S3     0x00000007      /* Bypass src2 and src3 */
197  
198  #define BLT_TTY_COL_SHIFT       16              /* Color format */
199  #define BLT_TTY_COL_MASK        0x001F0000      /* Color format mask */
200  #define BLT_TTY_ALPHA_R         BIT(21)         /* Alpha range */
201  #define BLT_TTY_CR_NOT_CB       BIT(22)         /* CR not Cb */
202  #define BLT_TTY_MB              BIT(23)         /* MB frame / field*/
203  #define BLT_TTY_HSO             BIT(24)         /* H scan order */
204  #define BLT_TTY_VSO             BIT(25)         /* V scan order */
205  #define BLT_TTY_DITHER          BIT(26)         /* Dithering */
206  #define BLT_TTY_CHROMA          BIT(27)         /* Write chroma / luma */
207  #define BLT_TTY_BIG_END         BIT(30)         /* Big endianness */
208  
209  #define BLT_S1TY_A1_SUBSET      BIT(22)         /* A1 subset */
210  #define BLT_S1TY_CHROMA_EXT     BIT(26)         /* Chroma Extended */
211  #define BTL_S1TY_SUBBYTE        BIT(28)         /* Sub-byte fmt, pixel order */
212  #define BLT_S1TY_RGB_EXP        BIT(29)         /* RGB expansion mode */
213  
214  #define BLT_S2TY_A1_SUBSET      BIT(22)         /* A1 subset */
215  #define BLT_S2TY_CHROMA_EXT     BIT(26)         /* Chroma Extended */
216  #define BTL_S2TY_SUBBYTE        BIT(28)         /* Sub-byte fmt, pixel order */
217  #define BLT_S2TY_RGB_EXP        BIT(29)         /* RGB expansion mode */
218  
219  #define BLT_S3TY_BLANK_ACC      BIT(26)         /* Blank access */
220  
221  #define BLT_FCTL_HV_SCALE       0x00000055      /* H/V resize + color filter */
222  #define BLT_FCTL_Y_HV_SCALE     0x33000000      /* Luma version */
223  
224  #define BLT_FCTL_HV_SAMPLE      0x00000044      /* H/V resize */
225  #define BLT_FCTL_Y_HV_SAMPLE    0x22000000      /* Luma version */
226  
227  #define BLT_RZI_DEFAULT         0x20003000      /* H/VNB_repeat = 3/2 */
228  
229  /* Color format */
230  #define BDISP_RGB565            0x00            /* RGB565 */
231  #define BDISP_RGB888            0x01            /* RGB888 */
232  #define BDISP_XRGB8888          0x02            /* RGB888_32 */
233  #define BDISP_ARGB8888          0x05            /* ARGB888 */
234  #define BDISP_NV12              0x16            /* YCbCr42x R2B */
235  #define BDISP_YUV_3B            0x1E            /* YUV (3 buffer) */
236