xref: /openbmc/linux/sound/soc/xtensa/xtfpga-i2s.c (revision cbde81bc)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Xtfpga I2S controller driver
4  *
5  * Copyright (c) 2014 Cadence Design Systems Inc.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <sound/pcm_params.h>
15 #include <sound/soc.h>
16 
17 #define DRV_NAME	"xtfpga-i2s"
18 
19 #define XTFPGA_I2S_VERSION	0x00
20 #define XTFPGA_I2S_CONFIG	0x04
21 #define XTFPGA_I2S_INT_MASK	0x08
22 #define XTFPGA_I2S_INT_STATUS	0x0c
23 #define XTFPGA_I2S_CHAN0_DATA	0x10
24 #define XTFPGA_I2S_CHAN1_DATA	0x14
25 #define XTFPGA_I2S_CHAN2_DATA	0x18
26 #define XTFPGA_I2S_CHAN3_DATA	0x1c
27 
28 #define XTFPGA_I2S_CONFIG_TX_ENABLE	0x1
29 #define XTFPGA_I2S_CONFIG_INT_ENABLE	0x2
30 #define XTFPGA_I2S_CONFIG_LEFT		0x4
31 #define XTFPGA_I2S_CONFIG_RATIO_BASE	8
32 #define XTFPGA_I2S_CONFIG_RATIO_MASK	0x0000ff00
33 #define XTFPGA_I2S_CONFIG_RES_BASE	16
34 #define XTFPGA_I2S_CONFIG_RES_MASK	0x003f0000
35 #define XTFPGA_I2S_CONFIG_LEVEL_BASE	24
36 #define XTFPGA_I2S_CONFIG_LEVEL_MASK	0x0f000000
37 #define XTFPGA_I2S_CONFIG_CHANNEL_BASE	28
38 
39 #define XTFPGA_I2S_INT_UNDERRUN		0x1
40 #define XTFPGA_I2S_INT_LEVEL		0x2
41 #define XTFPGA_I2S_INT_VALID		0x3
42 
43 #define XTFPGA_I2S_FIFO_SIZE		8192
44 
45 /*
46  * I2S controller operation:
47  *
48  * Enabling TX: output 1 period of zeros (starting with left channel)
49  * and then queued data.
50  *
51  * Level status and interrupt: whenever FIFO level is below FIFO trigger,
52  * level status is 1 and an IRQ is asserted (if enabled).
53  *
54  * Underrun status and interrupt: whenever FIFO is empty, underrun status
55  * is 1 and an IRQ is asserted (if enabled).
56  */
57 struct xtfpga_i2s {
58 	struct device *dev;
59 	struct clk *clk;
60 	struct regmap *regmap;
61 	void __iomem *regs;
62 
63 	/* current playback substream. NULL if not playing.
64 	 *
65 	 * Access to that field is synchronized between the interrupt handler
66 	 * and userspace through RCU.
67 	 *
68 	 * Interrupt handler (threaded part) does PIO on substream data in RCU
69 	 * read-side critical section. Trigger callback sets and clears the
70 	 * pointer when the playback is started and stopped with
71 	 * rcu_assign_pointer. When userspace is about to free the playback
72 	 * stream in the pcm_close callback it synchronizes with the interrupt
73 	 * handler by means of synchronize_rcu call.
74 	 */
75 	struct snd_pcm_substream __rcu *tx_substream;
76 	unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
77 			  struct snd_pcm_runtime *runtime,
78 			  unsigned tx_ptr);
79 	unsigned tx_ptr; /* next frame index in the sample buffer */
80 
81 	/* current fifo level estimate.
82 	 * Doesn't have to be perfectly accurate, but must be not less than
83 	 * the actual FIFO level in order to avoid stall on push attempt.
84 	 */
85 	unsigned tx_fifo_level;
86 
87 	/* FIFO level at which level interrupt occurs */
88 	unsigned tx_fifo_low;
89 
90 	/* maximal FIFO level */
91 	unsigned tx_fifo_high;
92 };
93 
xtfpga_i2s_wr_reg(struct device * dev,unsigned int reg)94 static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
95 {
96 	return reg >= XTFPGA_I2S_CONFIG;
97 }
98 
xtfpga_i2s_rd_reg(struct device * dev,unsigned int reg)99 static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
100 {
101 	return reg < XTFPGA_I2S_CHAN0_DATA;
102 }
103 
xtfpga_i2s_volatile_reg(struct device * dev,unsigned int reg)104 static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
105 {
106 	return reg == XTFPGA_I2S_INT_STATUS;
107 }
108 
109 static const struct regmap_config xtfpga_i2s_regmap_config = {
110 	.reg_bits = 32,
111 	.reg_stride = 4,
112 	.val_bits = 32,
113 	.max_register = XTFPGA_I2S_CHAN3_DATA,
114 	.writeable_reg = xtfpga_i2s_wr_reg,
115 	.readable_reg = xtfpga_i2s_rd_reg,
116 	.volatile_reg = xtfpga_i2s_volatile_reg,
117 	.cache_type = REGCACHE_FLAT,
118 };
119 
120 /* Generate functions that do PIO from TX DMA area to FIFO for all supported
121  * stream formats.
122  * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
123  * xtfpga_pcm_tx_2x16 for 16-bit stereo.
124  *
125  * FIFO consists of 32-bit words, one word per channel, always 2 channels.
126  * If I2S interface is configured with smaller sample resolution, only
127  * the LSB of each word is used.
128  */
129 #define xtfpga_pcm_tx_fn(channels, sample_bits) \
130 static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
131 	struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
132 	unsigned tx_ptr) \
133 { \
134 	const u##sample_bits (*p)[channels] = \
135 		(void *)runtime->dma_area; \
136 \
137 	for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
138 	     i2s->tx_fifo_level += 2) { \
139 		iowrite32(p[tx_ptr][0], \
140 			  i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
141 		iowrite32(p[tx_ptr][channels - 1], \
142 			  i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
143 		if (++tx_ptr >= runtime->buffer_size) \
144 			tx_ptr = 0; \
145 	} \
146 	return tx_ptr; \
147 }
148 
149 xtfpga_pcm_tx_fn(1, 16)
150 xtfpga_pcm_tx_fn(2, 16)
151 xtfpga_pcm_tx_fn(1, 32)
152 xtfpga_pcm_tx_fn(2, 32)
153 
154 #undef xtfpga_pcm_tx_fn
155 
xtfpga_pcm_push_tx(struct xtfpga_i2s * i2s)156 static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
157 {
158 	struct snd_pcm_substream *tx_substream;
159 	bool tx_active;
160 
161 	rcu_read_lock();
162 	tx_substream = rcu_dereference(i2s->tx_substream);
163 	tx_active = tx_substream && snd_pcm_running(tx_substream);
164 	if (tx_active) {
165 		unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
166 		unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
167 						 tx_ptr);
168 
169 		cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
170 	}
171 	rcu_read_unlock();
172 
173 	return tx_active;
174 }
175 
xtfpga_pcm_refill_fifo(struct xtfpga_i2s * i2s)176 static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
177 {
178 	unsigned int_status;
179 	unsigned i;
180 
181 	regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
182 		    &int_status);
183 
184 	for (i = 0; i < 2; ++i) {
185 		bool tx_active = xtfpga_pcm_push_tx(i2s);
186 
187 		regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
188 			     XTFPGA_I2S_INT_VALID);
189 		if (tx_active)
190 			regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
191 				    &int_status);
192 
193 		if (!tx_active ||
194 		    !(int_status & XTFPGA_I2S_INT_LEVEL))
195 			break;
196 
197 		/* After the push the level IRQ is still asserted,
198 		 * means FIFO level is below tx_fifo_low. Estimate
199 		 * it as tx_fifo_low.
200 		 */
201 		i2s->tx_fifo_level = i2s->tx_fifo_low;
202 	}
203 
204 	if (!(int_status & XTFPGA_I2S_INT_LEVEL))
205 		regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
206 			     XTFPGA_I2S_INT_VALID);
207 	else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
208 		regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
209 			     XTFPGA_I2S_INT_UNDERRUN);
210 
211 	if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
212 		regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
213 				   XTFPGA_I2S_CONFIG_INT_ENABLE |
214 				   XTFPGA_I2S_CONFIG_TX_ENABLE,
215 				   XTFPGA_I2S_CONFIG_INT_ENABLE |
216 				   XTFPGA_I2S_CONFIG_TX_ENABLE);
217 	else
218 		regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
219 				   XTFPGA_I2S_CONFIG_INT_ENABLE |
220 				   XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
221 }
222 
xtfpga_i2s_threaded_irq_handler(int irq,void * dev_id)223 static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
224 {
225 	struct xtfpga_i2s *i2s = dev_id;
226 	struct snd_pcm_substream *tx_substream;
227 	unsigned config, int_status, int_mask;
228 
229 	regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
230 	regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
231 	regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
232 
233 	if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
234 	    !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
235 		return IRQ_NONE;
236 
237 	/* Update FIFO level estimate in accordance with interrupt status
238 	 * register.
239 	 */
240 	if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
241 		i2s->tx_fifo_level = 0;
242 		regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
243 				   XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
244 	} else {
245 		/* The FIFO isn't empty, but is below tx_fifo_low. Estimate
246 		 * it as tx_fifo_low.
247 		 */
248 		i2s->tx_fifo_level = i2s->tx_fifo_low;
249 	}
250 
251 	rcu_read_lock();
252 	tx_substream = rcu_dereference(i2s->tx_substream);
253 
254 	if (tx_substream && snd_pcm_running(tx_substream)) {
255 		snd_pcm_period_elapsed(tx_substream);
256 		if (int_status & XTFPGA_I2S_INT_UNDERRUN)
257 			dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
258 					    __func__);
259 	}
260 	rcu_read_unlock();
261 
262 	/* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
263 	 * not empty.
264 	 */
265 	xtfpga_pcm_refill_fifo(i2s);
266 
267 	return IRQ_HANDLED;
268 }
269 
xtfpga_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)270 static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
271 			      struct snd_soc_dai *dai)
272 {
273 	struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
274 
275 	snd_soc_dai_set_dma_data(dai, substream, i2s);
276 	return 0;
277 }
278 
xtfpga_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)279 static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
280 				struct snd_pcm_hw_params *params,
281 				struct snd_soc_dai *dai)
282 {
283 	struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
284 	unsigned srate = params_rate(params);
285 	unsigned channels = params_channels(params);
286 	unsigned period_size = params_period_size(params);
287 	unsigned sample_size = snd_pcm_format_width(params_format(params));
288 	unsigned freq, ratio, level;
289 	int err;
290 
291 	regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
292 			   XTFPGA_I2S_CONFIG_RES_MASK,
293 			   sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
294 
295 	freq = 256 * srate;
296 	err = clk_set_rate(i2s->clk, freq);
297 	if (err < 0)
298 		return err;
299 
300 	/* ratio field of the config register controls MCLK->I2S clock
301 	 * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
302 	 *
303 	 * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
304 	 * and 2 for 16 bit stereo.
305 	 */
306 	ratio = (freq - (srate * sample_size * 8)) /
307 		(srate * sample_size * 4);
308 
309 	regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
310 			   XTFPGA_I2S_CONFIG_RATIO_MASK,
311 			   ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
312 
313 	i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
314 
315 	/* period_size * 2: FIFO always gets 2 samples per frame */
316 	for (level = 1;
317 	     i2s->tx_fifo_low / 2 >= period_size * 2 &&
318 	     level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
319 		      XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
320 		i2s->tx_fifo_low /= 2;
321 
322 	i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
323 
324 	regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
325 			   XTFPGA_I2S_CONFIG_LEVEL_MASK,
326 			   level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
327 
328 	dev_dbg(i2s->dev,
329 		"%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
330 		__func__, srate, channels, sample_size, period_size);
331 	dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
332 		__func__, freq, ratio, level);
333 
334 	return 0;
335 }
336 
xtfpga_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)337 static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
338 			      unsigned int fmt)
339 {
340 	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
341 		return -EINVAL;
342 	if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_BP_FP)
343 		return -EINVAL;
344 	if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
345 		return -EINVAL;
346 
347 	return 0;
348 }
349 
350 /* PCM */
351 
352 static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
353 	.info = SNDRV_PCM_INFO_INTERLEAVED |
354 		SNDRV_PCM_INFO_MMAP_VALID |
355 		SNDRV_PCM_INFO_BLOCK_TRANSFER,
356 	.formats		= SNDRV_PCM_FMTBIT_S16_LE |
357 				  SNDRV_PCM_FMTBIT_S32_LE,
358 	.channels_min		= 1,
359 	.channels_max		= 2,
360 	.period_bytes_min	= 2,
361 	.period_bytes_max	= XTFPGA_I2S_FIFO_SIZE / 2 * 8,
362 	.periods_min		= 2,
363 	.periods_max		= XTFPGA_I2S_FIFO_SIZE * 8 / 2,
364 	.buffer_bytes_max	= XTFPGA_I2S_FIFO_SIZE * 8,
365 	.fifo_size		= 16,
366 };
367 
xtfpga_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)368 static int xtfpga_pcm_open(struct snd_soc_component *component,
369 			   struct snd_pcm_substream *substream)
370 {
371 	struct snd_pcm_runtime *runtime = substream->runtime;
372 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
373 	void *p;
374 
375 	snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
376 	p = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
377 	runtime->private_data = p;
378 
379 	return 0;
380 }
381 
xtfpga_pcm_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)382 static int xtfpga_pcm_close(struct snd_soc_component *component,
383 			    struct snd_pcm_substream *substream)
384 {
385 	synchronize_rcu();
386 	return 0;
387 }
388 
xtfpga_pcm_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)389 static int xtfpga_pcm_hw_params(struct snd_soc_component *component,
390 				struct snd_pcm_substream *substream,
391 				struct snd_pcm_hw_params *hw_params)
392 {
393 	struct snd_pcm_runtime *runtime = substream->runtime;
394 	struct xtfpga_i2s *i2s = runtime->private_data;
395 	unsigned channels = params_channels(hw_params);
396 
397 	switch (channels) {
398 	case 1:
399 	case 2:
400 		break;
401 
402 	default:
403 		return -EINVAL;
404 
405 	}
406 
407 	switch (params_format(hw_params)) {
408 	case SNDRV_PCM_FORMAT_S16_LE:
409 		i2s->tx_fn = (channels == 1) ?
410 			xtfpga_pcm_tx_1x16 :
411 			xtfpga_pcm_tx_2x16;
412 		break;
413 
414 	case SNDRV_PCM_FORMAT_S32_LE:
415 		i2s->tx_fn = (channels == 1) ?
416 			xtfpga_pcm_tx_1x32 :
417 			xtfpga_pcm_tx_2x32;
418 		break;
419 
420 	default:
421 		return -EINVAL;
422 	}
423 
424 	return 0;
425 }
426 
xtfpga_pcm_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)427 static int xtfpga_pcm_trigger(struct snd_soc_component *component,
428 			      struct snd_pcm_substream *substream, int cmd)
429 {
430 	int ret = 0;
431 	struct snd_pcm_runtime *runtime = substream->runtime;
432 	struct xtfpga_i2s *i2s = runtime->private_data;
433 
434 	switch (cmd) {
435 	case SNDRV_PCM_TRIGGER_START:
436 	case SNDRV_PCM_TRIGGER_RESUME:
437 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
438 		WRITE_ONCE(i2s->tx_ptr, 0);
439 		rcu_assign_pointer(i2s->tx_substream, substream);
440 		xtfpga_pcm_refill_fifo(i2s);
441 		break;
442 
443 	case SNDRV_PCM_TRIGGER_STOP:
444 	case SNDRV_PCM_TRIGGER_SUSPEND:
445 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
446 		rcu_assign_pointer(i2s->tx_substream, NULL);
447 		break;
448 
449 	default:
450 		ret = -EINVAL;
451 		break;
452 	}
453 	return ret;
454 }
455 
xtfpga_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)456 static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
457 					    struct snd_pcm_substream *substream)
458 {
459 	struct snd_pcm_runtime *runtime = substream->runtime;
460 	struct xtfpga_i2s *i2s = runtime->private_data;
461 	snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
462 
463 	return pos < runtime->buffer_size ? pos : 0;
464 }
465 
xtfpga_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)466 static int xtfpga_pcm_new(struct snd_soc_component *component,
467 			  struct snd_soc_pcm_runtime *rtd)
468 {
469 	struct snd_card *card = rtd->card->snd_card;
470 	size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
471 
472 	snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
473 				       card->dev, size, size);
474 	return 0;
475 }
476 
477 static const struct snd_soc_component_driver xtfpga_i2s_component = {
478 	.name			= DRV_NAME,
479 	.open			= xtfpga_pcm_open,
480 	.close			= xtfpga_pcm_close,
481 	.hw_params		= xtfpga_pcm_hw_params,
482 	.trigger		= xtfpga_pcm_trigger,
483 	.pointer		= xtfpga_pcm_pointer,
484 	.pcm_construct		= xtfpga_pcm_new,
485 	.legacy_dai_naming	= 1,
486 };
487 
488 static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
489 	.startup	= xtfpga_i2s_startup,
490 	.hw_params      = xtfpga_i2s_hw_params,
491 	.set_fmt	= xtfpga_i2s_set_fmt,
492 };
493 
494 static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
495 	{
496 		.name = "xtfpga-i2s",
497 		.id = 0,
498 		.playback = {
499 			.channels_min = 1,
500 			.channels_max = 2,
501 			.rates = SNDRV_PCM_RATE_8000_96000,
502 			.formats = SNDRV_PCM_FMTBIT_S16_LE |
503 				   SNDRV_PCM_FMTBIT_S32_LE,
504 		},
505 		.ops = &xtfpga_i2s_dai_ops,
506 	},
507 };
508 
xtfpga_i2s_runtime_suspend(struct device * dev)509 static int xtfpga_i2s_runtime_suspend(struct device *dev)
510 {
511 	struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
512 
513 	clk_disable_unprepare(i2s->clk);
514 	return 0;
515 }
516 
xtfpga_i2s_runtime_resume(struct device * dev)517 static int xtfpga_i2s_runtime_resume(struct device *dev)
518 {
519 	struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
520 	int ret;
521 
522 	ret = clk_prepare_enable(i2s->clk);
523 	if (ret) {
524 		dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
525 		return ret;
526 	}
527 	return 0;
528 }
529 
xtfpga_i2s_probe(struct platform_device * pdev)530 static int xtfpga_i2s_probe(struct platform_device *pdev)
531 {
532 	struct xtfpga_i2s *i2s;
533 	int err, irq;
534 
535 	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
536 	if (!i2s) {
537 		err = -ENOMEM;
538 		goto err;
539 	}
540 	platform_set_drvdata(pdev, i2s);
541 	i2s->dev = &pdev->dev;
542 	dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
543 
544 	i2s->regs = devm_platform_ioremap_resource(pdev, 0);
545 	if (IS_ERR(i2s->regs)) {
546 		err = PTR_ERR(i2s->regs);
547 		goto err;
548 	}
549 
550 	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
551 					    &xtfpga_i2s_regmap_config);
552 	if (IS_ERR(i2s->regmap)) {
553 		dev_err(&pdev->dev, "regmap init failed\n");
554 		err = PTR_ERR(i2s->regmap);
555 		goto err;
556 	}
557 
558 	i2s->clk = devm_clk_get(&pdev->dev, NULL);
559 	if (IS_ERR(i2s->clk)) {
560 		dev_err(&pdev->dev, "couldn't get clock\n");
561 		err = PTR_ERR(i2s->clk);
562 		goto err;
563 	}
564 
565 	regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
566 		     (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
567 	regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
568 	regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
569 
570 	irq = platform_get_irq(pdev, 0);
571 	if (irq < 0) {
572 		err = irq;
573 		goto err;
574 	}
575 	err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
576 					xtfpga_i2s_threaded_irq_handler,
577 					IRQF_SHARED | IRQF_ONESHOT,
578 					pdev->name, i2s);
579 	if (err < 0) {
580 		dev_err(&pdev->dev, "request_irq failed\n");
581 		goto err;
582 	}
583 
584 	err = devm_snd_soc_register_component(&pdev->dev,
585 					      &xtfpga_i2s_component,
586 					      xtfpga_i2s_dai,
587 					      ARRAY_SIZE(xtfpga_i2s_dai));
588 	if (err < 0) {
589 		dev_err(&pdev->dev, "couldn't register component\n");
590 		goto err;
591 	}
592 
593 	pm_runtime_enable(&pdev->dev);
594 	if (!pm_runtime_enabled(&pdev->dev)) {
595 		err = xtfpga_i2s_runtime_resume(&pdev->dev);
596 		if (err)
597 			goto err_pm_disable;
598 	}
599 	return 0;
600 
601 err_pm_disable:
602 	pm_runtime_disable(&pdev->dev);
603 err:
604 	dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
605 	return err;
606 }
607 
xtfpga_i2s_remove(struct platform_device * pdev)608 static void xtfpga_i2s_remove(struct platform_device *pdev)
609 {
610 	struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
611 
612 	if (i2s->regmap && !IS_ERR(i2s->regmap)) {
613 		regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
614 		regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
615 		regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
616 			     XTFPGA_I2S_INT_VALID);
617 	}
618 	pm_runtime_disable(&pdev->dev);
619 	if (!pm_runtime_status_suspended(&pdev->dev))
620 		xtfpga_i2s_runtime_suspend(&pdev->dev);
621 }
622 
623 #ifdef CONFIG_OF
624 static const struct of_device_id xtfpga_i2s_of_match[] = {
625 	{ .compatible = "cdns,xtfpga-i2s", },
626 	{},
627 };
628 MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
629 #endif
630 
631 static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
632 	SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
633 			   xtfpga_i2s_runtime_resume, NULL)
634 };
635 
636 static struct platform_driver xtfpga_i2s_driver = {
637 	.probe   = xtfpga_i2s_probe,
638 	.remove_new = xtfpga_i2s_remove,
639 	.driver  = {
640 		.name = "xtfpga-i2s",
641 		.of_match_table = of_match_ptr(xtfpga_i2s_of_match),
642 		.pm = &xtfpga_i2s_pm_ops,
643 	},
644 };
645 
646 module_platform_driver(xtfpga_i2s_driver);
647 
648 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
649 MODULE_DESCRIPTION("xtfpga I2S controller driver");
650 MODULE_LICENSE("GPL v2");
651