1 /*
2 * QEMU Xtensa CPU
3 *
4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "cpu.h"
34 #include "fpu/softfloat.h"
35 #include "qemu/module.h"
36 #include "migration/vmstate.h"
37 #include "hw/qdev-clock.h"
38 #ifndef CONFIG_USER_ONLY
39 #include "exec/memory.h"
40 #endif
41
42
xtensa_cpu_set_pc(CPUState * cs,vaddr value)43 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
44 {
45 XtensaCPU *cpu = XTENSA_CPU(cs);
46
47 cpu->env.pc = value;
48 }
49
xtensa_cpu_get_pc(CPUState * cs)50 static vaddr xtensa_cpu_get_pc(CPUState *cs)
51 {
52 XtensaCPU *cpu = XTENSA_CPU(cs);
53
54 return cpu->env.pc;
55 }
56
xtensa_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)57 static void xtensa_restore_state_to_opc(CPUState *cs,
58 const TranslationBlock *tb,
59 const uint64_t *data)
60 {
61 XtensaCPU *cpu = XTENSA_CPU(cs);
62
63 cpu->env.pc = data[0];
64 }
65
66 #ifndef CONFIG_USER_ONLY
xtensa_cpu_has_work(CPUState * cs)67 static bool xtensa_cpu_has_work(CPUState *cs)
68 {
69 CPUXtensaState *env = cpu_env(cs);
70
71 return !env->runstall && env->pending_irq_level;
72 }
73 #endif /* !CONFIG_USER_ONLY */
74
xtensa_cpu_mmu_index(CPUState * cs,bool ifetch)75 static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch)
76 {
77 return xtensa_get_cring(cpu_env(cs));
78 }
79
80 #ifdef CONFIG_USER_ONLY
81 static bool abi_call0;
82
xtensa_set_abi_call0(void)83 void xtensa_set_abi_call0(void)
84 {
85 abi_call0 = true;
86 }
87
xtensa_abi_call0(void)88 bool xtensa_abi_call0(void)
89 {
90 return abi_call0;
91 }
92 #endif
93
xtensa_cpu_reset_hold(Object * obj,ResetType type)94 static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
95 {
96 CPUState *cs = CPU(obj);
97 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
98 CPUXtensaState *env = cpu_env(cs);
99 bool dfpu = xtensa_option_enabled(env->config,
100 XTENSA_OPTION_DFP_COPROCESSOR);
101
102 if (xcc->parent_phases.hold) {
103 xcc->parent_phases.hold(obj, type);
104 }
105
106 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
107 env->sregs[LITBASE] &= ~1;
108 #ifndef CONFIG_USER_ONLY
109 env->sregs[PS] = xtensa_option_enabled(env->config,
110 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
111 env->pending_irq_level = 0;
112 #else
113 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
114 if (xtensa_option_enabled(env->config,
115 XTENSA_OPTION_WINDOWED_REGISTER) &&
116 !xtensa_abi_call0()) {
117 env->sregs[PS] |= PS_WOE;
118 }
119 env->sregs[CPENABLE] = 0xff;
120 #endif
121 env->sregs[VECBASE] = env->config->vecbase;
122 env->sregs[IBREAKENABLE] = 0;
123 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
124 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
125 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
126 env->sregs[CONFIGID0] = env->config->configid[0];
127 env->sregs[CONFIGID1] = env->config->configid[1];
128 env->exclusive_addr = -1;
129
130 #ifndef CONFIG_USER_ONLY
131 reset_mmu(env);
132 cs->halted = env->runstall;
133 #endif
134 /* For inf * 0 + NaN, return the input NaN */
135 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
136 set_no_signaling_nans(!dfpu, &env->fp_status);
137 /* Default NaN value: sign bit clear, set frac msb */
138 set_float_default_nan_pattern(0b01000000, &env->fp_status);
139 xtensa_use_first_nan(env, !dfpu);
140 }
141
xtensa_cpu_class_by_name(const char * cpu_model)142 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
143 {
144 ObjectClass *oc;
145 char *typename;
146
147 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
148 oc = object_class_by_name(typename);
149 g_free(typename);
150
151 return oc;
152 }
153
xtensa_cpu_disas_set_info(CPUState * cs,disassemble_info * info)154 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
155 {
156 XtensaCPU *cpu = XTENSA_CPU(cs);
157
158 info->private_data = cpu->env.config->isa;
159 info->print_insn = print_insn_xtensa;
160 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
161 : BFD_ENDIAN_LITTLE;
162 }
163
xtensa_cpu_realizefn(DeviceState * dev,Error ** errp)164 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
165 {
166 CPUState *cs = CPU(dev);
167 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
168 Error *local_err = NULL;
169
170 #ifndef CONFIG_USER_ONLY
171 xtensa_irq_init(&XTENSA_CPU(dev)->env);
172 #endif
173
174 cpu_exec_realizefn(cs, &local_err);
175 if (local_err != NULL) {
176 error_propagate(errp, local_err);
177 return;
178 }
179
180 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
181
182 qemu_init_vcpu(cs);
183
184 xcc->parent_realize(dev, errp);
185 }
186
xtensa_cpu_initfn(Object * obj)187 static void xtensa_cpu_initfn(Object *obj)
188 {
189 XtensaCPU *cpu = XTENSA_CPU(obj);
190 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
191 CPUXtensaState *env = &cpu->env;
192
193 env->config = xcc->config;
194
195 #ifndef CONFIG_USER_ONLY
196 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
197 env->system_er = g_malloc(sizeof(*env->system_er));
198 memory_region_init_io(env->system_er, obj, NULL, env, "er",
199 UINT64_C(0x100000000));
200 address_space_init(env->address_space_er, env->system_er, "ER");
201
202 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
203 clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
204 #endif
205 }
206
xtensa_cpu_create_with_clock(const char * cpu_type,Clock * cpu_refclk)207 XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
208 {
209 DeviceState *cpu;
210
211 cpu = qdev_new(cpu_type);
212 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
213 qdev_realize(cpu, NULL, &error_abort);
214
215 return XTENSA_CPU(cpu);
216 }
217
218 #ifndef CONFIG_USER_ONLY
219 static const VMStateDescription vmstate_xtensa_cpu = {
220 .name = "cpu",
221 .unmigratable = 1,
222 };
223
224 #include "hw/core/sysemu-cpu-ops.h"
225
226 static const struct SysemuCPUOps xtensa_sysemu_ops = {
227 .has_work = xtensa_cpu_has_work,
228 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
229 };
230 #endif
231
232 #include "accel/tcg/cpu-ops.h"
233
234 static const TCGCPUOps xtensa_tcg_ops = {
235 .initialize = xtensa_translate_init,
236 .translate_code = xtensa_translate_code,
237 .debug_excp_handler = xtensa_breakpoint_handler,
238 .restore_state_to_opc = xtensa_restore_state_to_opc,
239
240 #ifndef CONFIG_USER_ONLY
241 .tlb_fill = xtensa_cpu_tlb_fill,
242 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
243 .cpu_exec_halt = xtensa_cpu_has_work,
244 .do_interrupt = xtensa_cpu_do_interrupt,
245 .do_transaction_failed = xtensa_cpu_do_transaction_failed,
246 .do_unaligned_access = xtensa_cpu_do_unaligned_access,
247 .debug_check_breakpoint = xtensa_debug_check_breakpoint,
248 #endif /* !CONFIG_USER_ONLY */
249 };
250
xtensa_cpu_class_init(ObjectClass * oc,void * data)251 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
252 {
253 DeviceClass *dc = DEVICE_CLASS(oc);
254 CPUClass *cc = CPU_CLASS(oc);
255 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
256 ResettableClass *rc = RESETTABLE_CLASS(oc);
257
258 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
259 &xcc->parent_realize);
260
261 resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
262 &xcc->parent_phases);
263
264 cc->class_by_name = xtensa_cpu_class_by_name;
265 cc->mmu_index = xtensa_cpu_mmu_index;
266 cc->dump_state = xtensa_cpu_dump_state;
267 cc->set_pc = xtensa_cpu_set_pc;
268 cc->get_pc = xtensa_cpu_get_pc;
269 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
270 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
271 cc->gdb_stop_before_watchpoint = true;
272 #ifndef CONFIG_USER_ONLY
273 cc->sysemu_ops = &xtensa_sysemu_ops;
274 dc->vmsd = &vmstate_xtensa_cpu;
275 #endif
276 cc->disas_set_info = xtensa_cpu_disas_set_info;
277 cc->tcg_ops = &xtensa_tcg_ops;
278 }
279
280 static const TypeInfo xtensa_cpu_type_info = {
281 .name = TYPE_XTENSA_CPU,
282 .parent = TYPE_CPU,
283 .instance_size = sizeof(XtensaCPU),
284 .instance_align = __alignof(XtensaCPU),
285 .instance_init = xtensa_cpu_initfn,
286 .abstract = true,
287 .class_size = sizeof(XtensaCPUClass),
288 .class_init = xtensa_cpu_class_init,
289 };
290
xtensa_cpu_register_types(void)291 static void xtensa_cpu_register_types(void)
292 {
293 type_register_static(&xtensa_cpu_type_info);
294 }
295
296 type_init(xtensa_cpu_register_types)
297