xref: /openbmc/linux/drivers/dma/sh/shdma.h (revision 6e400d6b)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Renesas SuperH DMA Engine support
4  *
5  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
7  *
8  */
9 #ifndef __DMA_SHDMA_H
10 #define __DMA_SHDMA_H
11 
12 #include <linux/sh_dma.h>
13 #include <linux/shdma-base.h>
14 #include <linux/dmaengine.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 
18 #define SH_DMAE_MAX_CHANNELS 20
19 #define SH_DMAE_TCR_MAX 0x00FFFFFF	/* 16MB */
20 
21 struct device;
22 
23 struct sh_dmae_chan {
24 	struct shdma_chan shdma_chan;
25 	const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
26 	int xmit_shift;			/* log_2(bytes_per_xfer) */
27 	void __iomem *base;
28 	char dev_id[32];		/* unique name per DMAC of channel */
29 	int pm_error;
30 	dma_addr_t slave_addr;
31 };
32 
33 struct sh_dmae_device {
34 	struct shdma_dev shdma_dev;
35 	struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
36 	const struct sh_dmae_pdata *pdata;
37 	struct list_head node;
38 	void __iomem *chan_reg;
39 	void __iomem *dmars;
40 	unsigned int chcr_offset;
41 	u32 chcr_ie_bit;
42 };
43 
44 struct sh_dmae_regs {
45 	u32 sar; /* SAR / source address */
46 	u32 dar; /* DAR / destination address */
47 	u32 tcr; /* TCR / transfer count */
48 };
49 
50 struct sh_dmae_desc {
51 	struct sh_dmae_regs hw;
52 	struct shdma_desc shdma_desc;
53 };
54 
55 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
56 #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
57 #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
58 #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
59 				     struct sh_dmae_device, shdma_dev.dma_dev)
60 
61 #endif	/* __DMA_SHDMA_H */
62