1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
14
15 #include "bcm-voter.h"
16 #include "icc-common.h"
17 #include "icc-rpmh.h"
18 #include "qdu1000.h"
19
20 static struct qcom_icc_node qup0_core_master = {
21 .name = "qup0_core_master",
22 .id = QDU1000_MASTER_QUP_CORE_0,
23 .channels = 1,
24 .buswidth = 4,
25 .num_links = 1,
26 .links = { QDU1000_SLAVE_QUP_CORE_0 },
27 };
28
29 static struct qcom_icc_node qup1_core_master = {
30 .name = "qup1_core_master",
31 .id = QDU1000_MASTER_QUP_CORE_1,
32 .channels = 1,
33 .buswidth = 4,
34 .num_links = 1,
35 .links = { QDU1000_SLAVE_QUP_CORE_1 },
36 };
37
38 static struct qcom_icc_node alm_sys_tcu = {
39 .name = "alm_sys_tcu",
40 .id = QDU1000_MASTER_SYS_TCU,
41 .channels = 1,
42 .buswidth = 8,
43 .num_links = 2,
44 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
45 };
46
47 static struct qcom_icc_node chm_apps = {
48 .name = "chm_apps",
49 .id = QDU1000_MASTER_APPSS_PROC,
50 .channels = 1,
51 .buswidth = 16,
52 .num_links = 4,
53 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
54 QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
55 },
56 };
57
58 static struct qcom_icc_node qnm_ecpri_dma = {
59 .name = "qnm_ecpri_dma",
60 .id = QDU1000_MASTER_GEMNOC_ECPRI_DMA,
61 .channels = 2,
62 .buswidth = 32,
63 .num_links = 2,
64 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
65 };
66
67 static struct qcom_icc_node qnm_fec_2_gemnoc = {
68 .name = "qnm_fec_2_gemnoc",
69 .id = QDU1000_MASTER_FEC_2_GEMNOC,
70 .channels = 2,
71 .buswidth = 32,
72 .num_links = 2,
73 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
74 };
75
76 static struct qcom_icc_node qnm_pcie = {
77 .name = "qnm_pcie",
78 .id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC,
79 .channels = 1,
80 .buswidth = 64,
81 .num_links = 3,
82 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
83 QDU1000_SLAVE_GEMNOC_MODEM_CNOC
84 },
85 };
86
87 static struct qcom_icc_node qnm_snoc_gc = {
88 .name = "qnm_snoc_gc",
89 .id = QDU1000_MASTER_SNOC_GC_MEM_NOC,
90 .channels = 1,
91 .buswidth = 8,
92 .num_links = 1,
93 .links = { QDU1000_SLAVE_LLCC },
94 };
95
96 static struct qcom_icc_node qnm_snoc_sf = {
97 .name = "qnm_snoc_sf",
98 .id = QDU1000_MASTER_SNOC_SF_MEM_NOC,
99 .channels = 1,
100 .buswidth = 16,
101 .num_links = 4,
102 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
103 QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
104 },
105 };
106
107 static struct qcom_icc_node qxm_mdsp = {
108 .name = "qxm_mdsp",
109 .id = QDU1000_MASTER_MSS_PROC,
110 .channels = 1,
111 .buswidth = 16,
112 .num_links = 3,
113 .links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
114 QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
115 },
116 };
117
118 static struct qcom_icc_node llcc_mc = {
119 .name = "llcc_mc",
120 .id = QDU1000_MASTER_LLCC,
121 .channels = 8,
122 .buswidth = 4,
123 .num_links = 1,
124 .links = { QDU1000_SLAVE_EBI1 },
125 };
126
127 static struct qcom_icc_node qhm_gic = {
128 .name = "qhm_gic",
129 .id = QDU1000_MASTER_GIC_AHB,
130 .channels = 1,
131 .buswidth = 4,
132 .num_links = 1,
133 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
134 };
135
136 static struct qcom_icc_node qhm_qdss_bam = {
137 .name = "qhm_qdss_bam",
138 .id = QDU1000_MASTER_QDSS_BAM,
139 .channels = 1,
140 .buswidth = 4,
141 .num_links = 1,
142 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
143 };
144
145 static struct qcom_icc_node qhm_qpic = {
146 .name = "qhm_qpic",
147 .id = QDU1000_MASTER_QPIC,
148 .channels = 1,
149 .buswidth = 4,
150 .num_links = 1,
151 .links = { QDU1000_SLAVE_A1NOC_SNOC },
152 };
153
154 static struct qcom_icc_node qhm_qspi = {
155 .name = "qhm_qspi",
156 .id = QDU1000_MASTER_QSPI_0,
157 .channels = 1,
158 .buswidth = 4,
159 .num_links = 1,
160 .links = { QDU1000_SLAVE_A1NOC_SNOC },
161 };
162
163 static struct qcom_icc_node qhm_qup0 = {
164 .name = "qhm_qup0",
165 .id = QDU1000_MASTER_QUP_0,
166 .channels = 1,
167 .buswidth = 4,
168 .num_links = 1,
169 .links = { QDU1000_SLAVE_A1NOC_SNOC },
170 };
171
172 static struct qcom_icc_node qhm_qup1 = {
173 .name = "qhm_qup1",
174 .id = QDU1000_MASTER_QUP_1,
175 .channels = 1,
176 .buswidth = 4,
177 .num_links = 1,
178 .links = { QDU1000_SLAVE_A1NOC_SNOC },
179 };
180
181 static struct qcom_icc_node qhm_system_noc_cfg = {
182 .name = "qhm_system_noc_cfg",
183 .id = QDU1000_MASTER_SNOC_CFG,
184 .channels = 1,
185 .buswidth = 4,
186 .num_links = 1,
187 .links = { QDU1000_SLAVE_SERVICE_SNOC },
188 };
189
190 static struct qcom_icc_node qnm_aggre_noc = {
191 .name = "qnm_aggre_noc",
192 .id = QDU1000_MASTER_ANOC_SNOC,
193 .channels = 1,
194 .buswidth = 8,
195 .num_links = 1,
196 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
197 };
198
199 static struct qcom_icc_node qnm_aggre_noc_gsi = {
200 .name = "qnm_aggre_noc_gsi",
201 .id = QDU1000_MASTER_ANOC_GSI,
202 .channels = 1,
203 .buswidth = 8,
204 .num_links = 1,
205 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
206 };
207
208 static struct qcom_icc_node qnm_gemnoc_cnoc = {
209 .name = "qnm_gemnoc_cnoc",
210 .id = QDU1000_MASTER_GEM_NOC_CNOC,
211 .channels = 1,
212 .buswidth = 16,
213 .num_links = 36,
214 .links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH,
215 QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS,
216 QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG,
217 QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG,
218 QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG,
219 QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS,
220 QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM,
221 QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG,
222 QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC,
223 QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0,
224 QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2,
225 QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG,
226 QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM,
227 QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG,
228 QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG,
229 QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM,
230 QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS,
231 QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU
232 },
233 };
234
235 static struct qcom_icc_node qnm_gemnoc_modem_slave = {
236 .name = "qnm_gemnoc_modem_slave",
237 .id = QDU1000_MASTER_GEMNOC_MODEM_CNOC,
238 .channels = 1,
239 .buswidth = 16,
240 .num_links = 1,
241 .links = { QDU1000_SLAVE_MODEM_OFFLINE },
242 };
243
244 static struct qcom_icc_node qnm_gemnoc_pcie = {
245 .name = "qnm_gemnoc_pcie",
246 .id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC,
247 .channels = 1,
248 .buswidth = 16,
249 .num_links = 1,
250 .links = { QDU1000_SLAVE_PCIE_0 },
251 };
252
253 static struct qcom_icc_node qxm_crypto = {
254 .name = "qxm_crypto",
255 .id = QDU1000_MASTER_CRYPTO,
256 .channels = 1,
257 .buswidth = 8,
258 .num_links = 1,
259 .links = { QDU1000_SLAVE_A1NOC_SNOC },
260 };
261
262 static struct qcom_icc_node qxm_ecpri_gsi = {
263 .name = "qxm_ecpri_gsi",
264 .id = QDU1000_MASTER_ECPRI_GSI,
265 .channels = 1,
266 .buswidth = 8,
267 .num_links = 2,
268 .links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 },
269 };
270
271 static struct qcom_icc_node qxm_pimem = {
272 .name = "qxm_pimem",
273 .id = QDU1000_MASTER_PIMEM,
274 .channels = 1,
275 .buswidth = 8,
276 .num_links = 1,
277 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
278 };
279
280 static struct qcom_icc_node xm_ecpri_dma = {
281 .name = "xm_ecpri_dma",
282 .id = QDU1000_MASTER_SNOC_ECPRI_DMA,
283 .channels = 2,
284 .buswidth = 32,
285 .num_links = 2,
286 .links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 },
287 };
288
289 static struct qcom_icc_node xm_gic = {
290 .name = "xm_gic",
291 .id = QDU1000_MASTER_GIC,
292 .channels = 1,
293 .buswidth = 8,
294 .num_links = 1,
295 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
296 };
297
298 static struct qcom_icc_node xm_pcie = {
299 .name = "xm_pcie",
300 .id = QDU1000_MASTER_PCIE,
301 .channels = 1,
302 .buswidth = 64,
303 .num_links = 1,
304 .links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC },
305 };
306
307 static struct qcom_icc_node xm_qdss_etr0 = {
308 .name = "xm_qdss_etr0",
309 .id = QDU1000_MASTER_QDSS_ETR,
310 .channels = 1,
311 .buswidth = 8,
312 .num_links = 1,
313 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
314 };
315
316 static struct qcom_icc_node xm_qdss_etr1 = {
317 .name = "xm_qdss_etr1",
318 .id = QDU1000_MASTER_QDSS_ETR_1,
319 .channels = 1,
320 .buswidth = 8,
321 .num_links = 1,
322 .links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
323 };
324
325 static struct qcom_icc_node xm_sdc = {
326 .name = "xm_sdc",
327 .id = QDU1000_MASTER_SDCC_1,
328 .channels = 1,
329 .buswidth = 8,
330 .num_links = 1,
331 .links = { QDU1000_SLAVE_A1NOC_SNOC },
332 };
333
334 static struct qcom_icc_node xm_usb3 = {
335 .name = "xm_usb3",
336 .id = QDU1000_MASTER_USB3,
337 .channels = 1,
338 .buswidth = 8,
339 .num_links = 1,
340 .links = { QDU1000_SLAVE_A1NOC_SNOC },
341 };
342
343 static struct qcom_icc_node qup0_core_slave = {
344 .name = "qup0_core_slave",
345 .id = QDU1000_SLAVE_QUP_CORE_0,
346 .channels = 1,
347 .buswidth = 4,
348 .num_links = 0,
349 };
350
351 static struct qcom_icc_node qup1_core_slave = {
352 .name = "qup1_core_slave",
353 .id = QDU1000_SLAVE_QUP_CORE_1,
354 .channels = 1,
355 .buswidth = 4,
356 .num_links = 0,
357 };
358
359 static struct qcom_icc_node qns_gem_noc_cnoc = {
360 .name = "qns_gem_noc_cnoc",
361 .id = QDU1000_SLAVE_GEM_NOC_CNOC,
362 .channels = 1,
363 .buswidth = 16,
364 .num_links = 1,
365 .links = { QDU1000_MASTER_GEM_NOC_CNOC },
366 };
367
368 static struct qcom_icc_node qns_llcc = {
369 .name = "qns_llcc",
370 .id = QDU1000_SLAVE_LLCC,
371 .channels = 8,
372 .buswidth = 16,
373 .num_links = 1,
374 .links = { QDU1000_MASTER_LLCC },
375 };
376
377 static struct qcom_icc_node qns_modem_slave = {
378 .name = "qns_modem_slave",
379 .id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC,
380 .channels = 1,
381 .buswidth = 16,
382 .num_links = 1,
383 .links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC },
384 };
385
386 static struct qcom_icc_node qns_pcie = {
387 .name = "qns_pcie",
388 .id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC,
389 .channels = 1,
390 .buswidth = 16,
391 .num_links = 1,
392 .links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC },
393 };
394
395 static struct qcom_icc_node ebi = {
396 .name = "ebi",
397 .id = QDU1000_SLAVE_EBI1,
398 .channels = 8,
399 .buswidth = 4,
400 .num_links = 0,
401 };
402
403 static struct qcom_icc_node qhs_ahb2phy0_south = {
404 .name = "qhs_ahb2phy0_south",
405 .id = QDU1000_SLAVE_AHB2PHY_SOUTH,
406 .channels = 1,
407 .buswidth = 4,
408 .num_links = 0,
409 };
410
411 static struct qcom_icc_node qhs_ahb2phy1_north = {
412 .name = "qhs_ahb2phy1_north",
413 .id = QDU1000_SLAVE_AHB2PHY_NORTH,
414 .channels = 1,
415 .buswidth = 4,
416 .num_links = 0,
417 };
418
419 static struct qcom_icc_node qhs_ahb2phy2_east = {
420 .name = "qhs_ahb2phy2_east",
421 .id = QDU1000_SLAVE_AHB2PHY_EAST,
422 .channels = 1,
423 .buswidth = 4,
424 .num_links = 0,
425 };
426
427 static struct qcom_icc_node qhs_aoss = {
428 .name = "qhs_aoss",
429 .id = QDU1000_SLAVE_AOSS,
430 .channels = 1,
431 .buswidth = 4,
432 .num_links = 0,
433 };
434
435 static struct qcom_icc_node qhs_clk_ctl = {
436 .name = "qhs_clk_ctl",
437 .id = QDU1000_SLAVE_CLK_CTL,
438 .channels = 1,
439 .buswidth = 4,
440 .num_links = 0,
441 };
442
443 static struct qcom_icc_node qhs_cpr_cx = {
444 .name = "qhs_cpr_cx",
445 .id = QDU1000_SLAVE_RBCPR_CX_CFG,
446 .channels = 1,
447 .buswidth = 4,
448 .num_links = 0,
449 };
450
451 static struct qcom_icc_node qhs_cpr_mx = {
452 .name = "qhs_cpr_mx",
453 .id = QDU1000_SLAVE_RBCPR_MX_CFG,
454 .channels = 1,
455 .buswidth = 4,
456 .num_links = 0,
457 };
458
459 static struct qcom_icc_node qhs_crypto_cfg = {
460 .name = "qhs_crypto_cfg",
461 .id = QDU1000_SLAVE_CRYPTO_0_CFG,
462 .channels = 1,
463 .buswidth = 4,
464 .num_links = 0,
465 };
466
467 static struct qcom_icc_node qhs_ecpri_cfg = {
468 .name = "qhs_ecpri_cfg",
469 .id = QDU1000_SLAVE_ECPRI_CFG,
470 .channels = 1,
471 .buswidth = 4,
472 .num_links = 0,
473 };
474
475 static struct qcom_icc_node qhs_imem_cfg = {
476 .name = "qhs_imem_cfg",
477 .id = QDU1000_SLAVE_IMEM_CFG,
478 .channels = 1,
479 .buswidth = 4,
480 .num_links = 0,
481 };
482
483 static struct qcom_icc_node qhs_ipc_router = {
484 .name = "qhs_ipc_router",
485 .id = QDU1000_SLAVE_IPC_ROUTER_CFG,
486 .channels = 1,
487 .buswidth = 4,
488 .num_links = 0,
489 };
490
491 static struct qcom_icc_node qhs_mss_cfg = {
492 .name = "qhs_mss_cfg",
493 .id = QDU1000_SLAVE_CNOC_MSS,
494 .channels = 1,
495 .buswidth = 4,
496 .num_links = 0,
497 };
498
499 static struct qcom_icc_node qhs_pcie_cfg = {
500 .name = "qhs_pcie_cfg",
501 .id = QDU1000_SLAVE_PCIE_CFG,
502 .channels = 1,
503 .buswidth = 4,
504 .num_links = 0,
505 };
506
507 static struct qcom_icc_node qhs_pdm = {
508 .name = "qhs_pdm",
509 .id = QDU1000_SLAVE_PDM,
510 .channels = 1,
511 .buswidth = 4,
512 .num_links = 0,
513 };
514
515 static struct qcom_icc_node qhs_pimem_cfg = {
516 .name = "qhs_pimem_cfg",
517 .id = QDU1000_SLAVE_PIMEM_CFG,
518 .channels = 1,
519 .buswidth = 4,
520 .num_links = 0,
521 };
522
523 static struct qcom_icc_node qhs_prng = {
524 .name = "qhs_prng",
525 .id = QDU1000_SLAVE_PRNG,
526 .channels = 1,
527 .buswidth = 4,
528 .num_links = 0,
529 };
530
531 static struct qcom_icc_node qhs_qdss_cfg = {
532 .name = "qhs_qdss_cfg",
533 .id = QDU1000_SLAVE_QDSS_CFG,
534 .channels = 1,
535 .buswidth = 4,
536 .num_links = 0,
537 };
538
539 static struct qcom_icc_node qhs_qpic = {
540 .name = "qhs_qpic",
541 .id = QDU1000_SLAVE_QPIC,
542 .channels = 1,
543 .buswidth = 4,
544 .num_links = 0,
545 };
546
547 static struct qcom_icc_node qhs_qspi = {
548 .name = "qhs_qspi",
549 .id = QDU1000_SLAVE_QSPI_0,
550 .channels = 1,
551 .buswidth = 4,
552 .num_links = 0,
553 };
554
555 static struct qcom_icc_node qhs_qup0 = {
556 .name = "qhs_qup0",
557 .id = QDU1000_SLAVE_QUP_0,
558 .channels = 1,
559 .buswidth = 4,
560 .num_links = 0,
561 };
562
563 static struct qcom_icc_node qhs_qup1 = {
564 .name = "qhs_qup1",
565 .id = QDU1000_SLAVE_QUP_1,
566 .channels = 1,
567 .buswidth = 4,
568 .num_links = 0,
569 };
570
571 static struct qcom_icc_node qhs_sdc2 = {
572 .name = "qhs_sdc2",
573 .id = QDU1000_SLAVE_SDCC_2,
574 .channels = 1,
575 .buswidth = 4,
576 .num_links = 0,
577 };
578
579 static struct qcom_icc_node qhs_smbus_cfg = {
580 .name = "qhs_smbus_cfg",
581 .id = QDU1000_SLAVE_SMBUS_CFG,
582 .channels = 1,
583 .buswidth = 4,
584 .num_links = 0,
585 };
586
587 static struct qcom_icc_node qhs_system_noc_cfg = {
588 .name = "qhs_system_noc_cfg",
589 .id = QDU1000_SLAVE_SNOC_CFG,
590 .channels = 1,
591 .buswidth = 4,
592 .num_links = 1,
593 .links = { QDU1000_MASTER_SNOC_CFG },
594 };
595
596 static struct qcom_icc_node qhs_tcsr = {
597 .name = "qhs_tcsr",
598 .id = QDU1000_SLAVE_TCSR,
599 .channels = 1,
600 .buswidth = 4,
601 .num_links = 0,
602 };
603
604 static struct qcom_icc_node qhs_tlmm = {
605 .name = "qhs_tlmm",
606 .id = QDU1000_SLAVE_TLMM,
607 .channels = 1,
608 .buswidth = 4,
609 .num_links = 0,
610 };
611
612 static struct qcom_icc_node qhs_tme_cfg = {
613 .name = "qhs_tme_cfg",
614 .id = QDU1000_SLAVE_TME_CFG,
615 .channels = 1,
616 .buswidth = 4,
617 .num_links = 0,
618 };
619
620 static struct qcom_icc_node qhs_tsc_cfg = {
621 .name = "qhs_tsc_cfg",
622 .id = QDU1000_SLAVE_TSC_CFG,
623 .channels = 1,
624 .buswidth = 4,
625 .num_links = 0,
626 };
627
628 static struct qcom_icc_node qhs_usb3 = {
629 .name = "qhs_usb3",
630 .id = QDU1000_SLAVE_USB3_0,
631 .channels = 1,
632 .buswidth = 4,
633 .num_links = 0,
634 };
635
636 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
637 .name = "qhs_vsense_ctrl_cfg",
638 .id = QDU1000_SLAVE_VSENSE_CTRL_CFG,
639 .channels = 1,
640 .buswidth = 4,
641 .num_links = 0,
642 };
643
644 static struct qcom_icc_node qns_a1noc_snoc = {
645 .name = "qns_a1noc_snoc",
646 .id = QDU1000_SLAVE_A1NOC_SNOC,
647 .channels = 1,
648 .buswidth = 8,
649 .num_links = 1,
650 .links = { QDU1000_MASTER_ANOC_SNOC },
651 };
652
653 static struct qcom_icc_node qns_anoc_snoc_gsi = {
654 .name = "qns_anoc_snoc_gsi",
655 .id = QDU1000_SLAVE_ANOC_SNOC_GSI,
656 .channels = 1,
657 .buswidth = 8,
658 .num_links = 1,
659 .links = { QDU1000_MASTER_ANOC_GSI },
660 };
661
662 static struct qcom_icc_node qns_ddrss_cfg = {
663 .name = "qns_ddrss_cfg",
664 .id = QDU1000_SLAVE_DDRSS_CFG,
665 .channels = 1,
666 .buswidth = 4,
667 .num_links = 0,
668 };
669
670 static struct qcom_icc_node qns_ecpri_gemnoc = {
671 .name = "qns_ecpri_gemnoc",
672 .id = QDU1000_SLAVE_ECPRI_GEMNOC,
673 .channels = 2,
674 .buswidth = 32,
675 .num_links = 1,
676 .links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA },
677 };
678
679 static struct qcom_icc_node qns_gemnoc_gc = {
680 .name = "qns_gemnoc_gc",
681 .id = QDU1000_SLAVE_SNOC_GEM_NOC_GC,
682 .channels = 1,
683 .buswidth = 8,
684 .num_links = 1,
685 .links = { QDU1000_MASTER_SNOC_GC_MEM_NOC },
686 };
687
688 static struct qcom_icc_node qns_gemnoc_sf = {
689 .name = "qns_gemnoc_sf",
690 .id = QDU1000_SLAVE_SNOC_GEM_NOC_SF,
691 .channels = 1,
692 .buswidth = 16,
693 .num_links = 1,
694 .links = { QDU1000_MASTER_SNOC_SF_MEM_NOC },
695 };
696
697 static struct qcom_icc_node qns_modem = {
698 .name = "qns_modem",
699 .id = QDU1000_SLAVE_MODEM_OFFLINE,
700 .channels = 1,
701 .buswidth = 32,
702 .num_links = 0,
703 };
704
705 static struct qcom_icc_node qns_pcie_gemnoc = {
706 .name = "qns_pcie_gemnoc",
707 .id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC,
708 .channels = 1,
709 .buswidth = 64,
710 .num_links = 1,
711 .links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC },
712 };
713
714 static struct qcom_icc_node qxs_imem = {
715 .name = "qxs_imem",
716 .id = QDU1000_SLAVE_IMEM,
717 .channels = 1,
718 .buswidth = 8,
719 .num_links = 0,
720 };
721
722 static struct qcom_icc_node qxs_pimem = {
723 .name = "qxs_pimem",
724 .id = QDU1000_SLAVE_PIMEM,
725 .channels = 1,
726 .buswidth = 8,
727 .num_links = 0,
728 };
729
730 static struct qcom_icc_node srvc_system_noc = {
731 .name = "srvc_system_noc",
732 .id = QDU1000_SLAVE_SERVICE_SNOC,
733 .channels = 1,
734 .buswidth = 4,
735 .num_links = 0,
736 };
737
738 static struct qcom_icc_node xs_ethernet_ss = {
739 .name = "xs_ethernet_ss",
740 .id = QDU1000_SLAVE_ETHERNET_SS,
741 .channels = 1,
742 .buswidth = 32,
743 .num_links = 0,
744 };
745
746 static struct qcom_icc_node xs_pcie = {
747 .name = "xs_pcie",
748 .id = QDU1000_SLAVE_PCIE_0,
749 .channels = 1,
750 .buswidth = 64,
751 .num_links = 0,
752 };
753
754 static struct qcom_icc_node xs_qdss_stm = {
755 .name = "xs_qdss_stm",
756 .id = QDU1000_SLAVE_QDSS_STM,
757 .channels = 1,
758 .buswidth = 4,
759 .num_links = 0,
760 };
761
762 static struct qcom_icc_node xs_sys_tcu_cfg = {
763 .name = "xs_sys_tcu_cfg",
764 .id = QDU1000_SLAVE_TCU,
765 .channels = 1,
766 .buswidth = 8,
767 .num_links = 0,
768 };
769
770 static struct qcom_icc_bcm bcm_acv = {
771 .name = "ACV",
772 .enable_mask = BIT(3),
773 .num_nodes = 1,
774 .nodes = { &ebi },
775 };
776
777 static struct qcom_icc_bcm bcm_ce0 = {
778 .name = "CE0",
779 .num_nodes = 1,
780 .nodes = { &qxm_crypto },
781 };
782
783 static struct qcom_icc_bcm bcm_cn0 = {
784 .name = "CN0",
785 .num_nodes = 44,
786 .nodes = { &qhm_qpic, &qhm_qspi,
787 &qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave,
788 &qnm_gemnoc_pcie, &xm_sdc,
789 &xm_usb3, &qhs_ahb2phy0_south,
790 &qhs_ahb2phy1_north, &qhs_ahb2phy2_east,
791 &qhs_aoss, &qhs_clk_ctl,
792 &qhs_cpr_cx, &qhs_cpr_mx,
793 &qhs_crypto_cfg, &qhs_ecpri_cfg,
794 &qhs_imem_cfg, &qhs_ipc_router,
795 &qhs_mss_cfg, &qhs_pcie_cfg,
796 &qhs_pdm, &qhs_pimem_cfg,
797 &qhs_prng, &qhs_qdss_cfg,
798 &qhs_qpic, &qhs_qspi,
799 &qhs_qup0, &qhs_qup1,
800 &qhs_sdc2, &qhs_smbus_cfg,
801 &qhs_system_noc_cfg, &qhs_tcsr,
802 &qhs_tlmm, &qhs_tme_cfg,
803 &qhs_tsc_cfg, &qhs_usb3,
804 &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
805 &qns_modem, &qxs_imem,
806 &qxs_pimem, &xs_ethernet_ss,
807 &xs_qdss_stm, &xs_sys_tcu_cfg
808 },
809 };
810
811 static struct qcom_icc_bcm bcm_mc0 = {
812 .name = "MC0",
813 .num_nodes = 1,
814 .nodes = { &ebi },
815 };
816
817 static struct qcom_icc_bcm bcm_qup0 = {
818 .name = "QUP0",
819 .num_nodes = 2,
820 .nodes = { &qup0_core_slave, &qup1_core_slave },
821 };
822
823 static struct qcom_icc_bcm bcm_sh0 = {
824 .name = "SH0",
825 .num_nodes = 1,
826 .nodes = { &qns_llcc },
827 };
828
829 static struct qcom_icc_bcm bcm_sh1 = {
830 .name = "SH1",
831 .num_nodes = 11,
832 .nodes = { &alm_sys_tcu, &chm_apps,
833 &qnm_ecpri_dma, &qnm_fec_2_gemnoc,
834 &qnm_pcie, &qnm_snoc_gc,
835 &qnm_snoc_sf, &qxm_mdsp,
836 &qns_gem_noc_cnoc, &qns_modem_slave,
837 &qns_pcie
838 },
839 };
840
841 static struct qcom_icc_bcm bcm_sn0 = {
842 .name = "SN0",
843 .num_nodes = 1,
844 .nodes = { &qns_gemnoc_sf },
845 };
846
847 static struct qcom_icc_bcm bcm_sn1 = {
848 .name = "SN1",
849 .num_nodes = 6,
850 .nodes = { &qhm_gic, &qxm_pimem,
851 &xm_gic, &xm_qdss_etr0,
852 &xm_qdss_etr1, &qns_gemnoc_gc
853 },
854 };
855
856 static struct qcom_icc_bcm bcm_sn2 = {
857 .name = "SN2",
858 .num_nodes = 5,
859 .nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi,
860 &xm_ecpri_dma, &qns_anoc_snoc_gsi,
861 &qns_ecpri_gemnoc
862 },
863 };
864
865 static struct qcom_icc_bcm bcm_sn7 = {
866 .name = "SN7",
867 .num_nodes = 2,
868 .nodes = { &qns_pcie_gemnoc, &xs_pcie },
869 };
870
871 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
872 &bcm_qup0,
873 };
874
875 static struct qcom_icc_node * const clk_virt_nodes[] = {
876 [MASTER_QUP_CORE_0] = &qup0_core_master,
877 [MASTER_QUP_CORE_1] = &qup1_core_master,
878 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
879 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
880 };
881
882 static const struct qcom_icc_desc qdu1000_clk_virt = {
883 .nodes = clk_virt_nodes,
884 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
885 .bcms = clk_virt_bcms,
886 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
887 };
888
889 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
890 &bcm_sh0,
891 &bcm_sh1,
892 };
893
894 static struct qcom_icc_node * const gem_noc_nodes[] = {
895 [MASTER_SYS_TCU] = &alm_sys_tcu,
896 [MASTER_APPSS_PROC] = &chm_apps,
897 [MASTER_GEMNOC_ECPRI_DMA] = &qnm_ecpri_dma,
898 [MASTER_FEC_2_GEMNOC] = &qnm_fec_2_gemnoc,
899 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
900 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
901 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
902 [MASTER_MSS_PROC] = &qxm_mdsp,
903 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
904 [SLAVE_LLCC] = &qns_llcc,
905 [SLAVE_GEMNOC_MODEM_CNOC] = &qns_modem_slave,
906 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
907 };
908
909 static const struct qcom_icc_desc qdu1000_gem_noc = {
910 .nodes = gem_noc_nodes,
911 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
912 .bcms = gem_noc_bcms,
913 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
914 };
915
916 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
917 &bcm_acv,
918 &bcm_mc0,
919 };
920
921 static struct qcom_icc_node * const mc_virt_nodes[] = {
922 [MASTER_LLCC] = &llcc_mc,
923 [SLAVE_EBI1] = &ebi,
924 };
925
926 static const struct qcom_icc_desc qdu1000_mc_virt = {
927 .nodes = mc_virt_nodes,
928 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
929 .bcms = mc_virt_bcms,
930 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
931 };
932
933 static struct qcom_icc_bcm * const system_noc_bcms[] = {
934 &bcm_ce0,
935 &bcm_cn0,
936 &bcm_sn0,
937 &bcm_sn1,
938 &bcm_sn2,
939 &bcm_sn7,
940 };
941
942 static struct qcom_icc_node * const system_noc_nodes[] = {
943 [MASTER_GIC_AHB] = &qhm_gic,
944 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
945 [MASTER_QPIC] = &qhm_qpic,
946 [MASTER_QSPI_0] = &qhm_qspi,
947 [MASTER_QUP_0] = &qhm_qup0,
948 [MASTER_QUP_1] = &qhm_qup1,
949 [MASTER_SNOC_CFG] = &qhm_system_noc_cfg,
950 [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
951 [MASTER_ANOC_GSI] = &qnm_aggre_noc_gsi,
952 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
953 [MASTER_GEMNOC_MODEM_CNOC] = &qnm_gemnoc_modem_slave,
954 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
955 [MASTER_CRYPTO] = &qxm_crypto,
956 [MASTER_ECPRI_GSI] = &qxm_ecpri_gsi,
957 [MASTER_PIMEM] = &qxm_pimem,
958 [MASTER_SNOC_ECPRI_DMA] = &xm_ecpri_dma,
959 [MASTER_GIC] = &xm_gic,
960 [MASTER_PCIE] = &xm_pcie,
961 [MASTER_QDSS_ETR] = &xm_qdss_etr0,
962 [MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
963 [MASTER_SDCC_1] = &xm_sdc,
964 [MASTER_USB3] = &xm_usb3,
965 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0_south,
966 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1_north,
967 [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy2_east,
968 [SLAVE_AOSS] = &qhs_aoss,
969 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
970 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
971 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
972 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
973 [SLAVE_ECPRI_CFG] = &qhs_ecpri_cfg,
974 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
975 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
976 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
977 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
978 [SLAVE_PDM] = &qhs_pdm,
979 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
980 [SLAVE_PRNG] = &qhs_prng,
981 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
982 [SLAVE_QPIC] = &qhs_qpic,
983 [SLAVE_QSPI_0] = &qhs_qspi,
984 [SLAVE_QUP_0] = &qhs_qup0,
985 [SLAVE_QUP_1] = &qhs_qup1,
986 [SLAVE_SDCC_2] = &qhs_sdc2,
987 [SLAVE_SMBUS_CFG] = &qhs_smbus_cfg,
988 [SLAVE_SNOC_CFG] = &qhs_system_noc_cfg,
989 [SLAVE_TCSR] = &qhs_tcsr,
990 [SLAVE_TLMM] = &qhs_tlmm,
991 [SLAVE_TME_CFG] = &qhs_tme_cfg,
992 [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
993 [SLAVE_USB3_0] = &qhs_usb3,
994 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
995 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
996 [SLAVE_ANOC_SNOC_GSI] = &qns_anoc_snoc_gsi,
997 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
998 [SLAVE_ECPRI_GEMNOC] = &qns_ecpri_gemnoc,
999 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1000 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1001 [SLAVE_MODEM_OFFLINE] = &qns_modem,
1002 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
1003 [SLAVE_IMEM] = &qxs_imem,
1004 [SLAVE_PIMEM] = &qxs_pimem,
1005 [SLAVE_SERVICE_SNOC] = &srvc_system_noc,
1006 [SLAVE_ETHERNET_SS] = &xs_ethernet_ss,
1007 [SLAVE_PCIE_0] = &xs_pcie,
1008 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1009 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1010 };
1011
1012 static const struct qcom_icc_desc qdu1000_system_noc = {
1013 .nodes = system_noc_nodes,
1014 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1015 .bcms = system_noc_bcms,
1016 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1017 };
1018
qnoc_probe(struct platform_device * pdev)1019 static int qnoc_probe(struct platform_device *pdev)
1020 {
1021 int ret;
1022
1023 ret = qcom_icc_rpmh_probe(pdev);
1024 if (ret)
1025 dev_err(&pdev->dev, "failed to register ICC provider\n");
1026
1027 return ret;
1028 }
1029
1030 static const struct of_device_id qnoc_of_match[] = {
1031 { .compatible = "qcom,qdu1000-clk-virt",
1032 .data = &qdu1000_clk_virt
1033 },
1034 { .compatible = "qcom,qdu1000-gem-noc",
1035 .data = &qdu1000_gem_noc
1036 },
1037 { .compatible = "qcom,qdu1000-mc-virt",
1038 .data = &qdu1000_mc_virt
1039 },
1040 { .compatible = "qcom,qdu1000-system-noc",
1041 .data = &qdu1000_system_noc
1042 },
1043 { }
1044 };
1045 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1046
1047 static struct platform_driver qnoc_driver = {
1048 .probe = qnoc_probe,
1049 .remove = qcom_icc_rpmh_remove,
1050 .driver = {
1051 .name = "qnoc-qdu1000",
1052 .of_match_table = qnoc_of_match,
1053 },
1054 };
1055
qnoc_driver_init(void)1056 static int __init qnoc_driver_init(void)
1057 {
1058 return platform_driver_register(&qnoc_driver);
1059 }
1060 core_initcall(qnoc_driver_init);
1061
qnoc_driver_exit(void)1062 static void __exit qnoc_driver_exit(void)
1063 {
1064 platform_driver_unregister(&qnoc_driver);
1065 }
1066 module_exit(qnoc_driver_exit);
1067
1068 MODULE_DESCRIPTION("QDU1000 NoC driver");
1069 MODULE_LICENSE("GPL");
1070