1 /*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2024, IBM Corporation..
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "qemu/log.h"
11 #include "qemu/module.h"
12 #include "qapi/error.h"
13 #include "target/ppc/cpu.h"
14 #include "system/cpus.h"
15 #include "system/dma.h"
16 #include "hw/qdev-properties.h"
17 #include "hw/ppc/xive.h"
18 #include "hw/ppc/xive2.h"
19 #include "hw/ppc/xive2_regs.h"
20 #include "trace.h"
21
22 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
23 uint32_t end_idx, uint32_t end_data,
24 bool redistribute);
25
26 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring,
27 uint8_t *nvp_blk, uint32_t *nvp_idx);
28
xive2_router_get_config(Xive2Router * xrtr)29 uint32_t xive2_router_get_config(Xive2Router *xrtr)
30 {
31 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
32
33 return xrc->get_config(xrtr);
34 }
35
xive2_router_get_block_id(Xive2Router * xrtr)36 static int xive2_router_get_block_id(Xive2Router *xrtr)
37 {
38 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
39
40 return xrc->get_block_id(xrtr);
41 }
42
xive2_nvp_reporting_addr(Xive2Nvp * nvp)43 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp)
44 {
45 uint64_t cache_addr;
46
47 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 |
48 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7);
49 cache_addr <<= 8; /* aligned on a cache line pair */
50 return cache_addr;
51 }
52
xive2_nvgc_get_backlog(Xive2Nvgc * nvgc,uint8_t priority)53 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority)
54 {
55 uint32_t val = 0;
56 uint8_t *ptr, i;
57
58 if (priority > 7) {
59 return 0;
60 }
61
62 /*
63 * The per-priority backlog counters are 24-bit and the structure
64 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from
65 * w2, which fits 8 priorities * 24-bits per priority.
66 */
67 ptr = (uint8_t *)&nvgc->w2 + priority * 3;
68 for (i = 0; i < 3; i++, ptr++) {
69 val = (val << 8) + *ptr;
70 }
71 return val;
72 }
73
xive2_nvgc_set_backlog(Xive2Nvgc * nvgc,uint8_t priority,uint32_t val)74 static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority,
75 uint32_t val)
76 {
77 uint8_t *ptr, i;
78 uint32_t shift;
79
80 if (priority > 7) {
81 return;
82 }
83
84 if (val > 0xFFFFFF) {
85 val = 0xFFFFFF;
86 }
87 /*
88 * The per-priority backlog counters are 24-bit and the structure
89 * is stored in big endian
90 */
91 ptr = (uint8_t *)&nvgc->w2 + priority * 3;
92 for (i = 0; i < 3; i++, ptr++) {
93 shift = 8 * (2 - i);
94 *ptr = (val >> shift) & 0xFF;
95 }
96 }
97
xive2_presenter_nvgc_backlog_op(XivePresenter * xptr,bool crowd,uint8_t blk,uint32_t idx,uint16_t offset,uint16_t val)98 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
99 bool crowd,
100 uint8_t blk, uint32_t idx,
101 uint16_t offset, uint16_t val)
102 {
103 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
104 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset);
105 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset);
106 Xive2Nvgc nvgc;
107 uint32_t count, old_count;
108
109 if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) {
110 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n",
111 crowd ? "NVC" : "NVG", blk, idx);
112 return -1;
113 }
114 if (!xive2_nvgc_is_valid(&nvgc)) {
115 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx);
116 return -1;
117 }
118
119 old_count = xive2_nvgc_get_backlog(&nvgc, priority);
120 count = old_count;
121 /*
122 * op:
123 * 0b00 => increment
124 * 0b01 => decrement
125 * 0b1- => read
126 */
127 if (op == 0b00 || op == 0b01) {
128 if (op == 0b00) {
129 count += val;
130 } else {
131 if (count > val) {
132 count -= val;
133 } else {
134 count = 0;
135 }
136 }
137 xive2_nvgc_set_backlog(&nvgc, priority, count);
138 xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc);
139 }
140 trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count);
141 return old_count;
142 }
143
xive2_presenter_nvp_backlog_op(XivePresenter * xptr,uint8_t blk,uint32_t idx,uint16_t offset)144 uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
145 uint8_t blk, uint32_t idx,
146 uint16_t offset)
147 {
148 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
149 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset);
150 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset);
151 Xive2Nvp nvp;
152 uint8_t ipb, old_ipb, rc;
153
154 if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) {
155 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx);
156 return -1;
157 }
158 if (!xive2_nvp_is_valid(&nvp)) {
159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx);
160 return -1;
161 }
162
163 old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
164 ipb = old_ipb;
165 /*
166 * op:
167 * 0b00 => set priority bit
168 * 0b01 => reset priority bit
169 * 0b1- => read
170 */
171 if (op == 0b00 || op == 0b01) {
172 if (op == 0b00) {
173 ipb |= xive_priority_to_ipb(priority);
174 } else {
175 ipb &= ~xive_priority_to_ipb(priority);
176 }
177 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
178 xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2);
179 }
180 rc = !!(old_ipb & xive_priority_to_ipb(priority));
181 trace_xive_nvp_backlog_op(blk, idx, op, priority, rc);
182 return rc;
183 }
184
xive2_eas_pic_print_info(Xive2Eas * eas,uint32_t lisn,GString * buf)185 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
186 {
187 if (!xive2_eas_is_valid(eas)) {
188 return;
189 }
190
191 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n",
192 lisn, xive2_eas_is_masked(eas) ? "M" : " ",
193 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
194 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
195 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
196 }
197
198 #define XIVE2_QSIZE_CHUNK_CL 128
199 #define XIVE2_QSIZE_CHUNK_4k 4096
200 /* Calculate max number of queue entries for an END */
xive2_end_get_qentries(Xive2End * end)201 static uint32_t xive2_end_get_qentries(Xive2End *end)
202 {
203 uint32_t w3 = end->w3;
204 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, w3);
205 if (xive_get_field32(END2_W3_CL, w3)) {
206 g_assert(qsize <= 4);
207 return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t);
208 } else {
209 g_assert(qsize <= 12);
210 return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t);
211 }
212 }
213
xive2_end_queue_pic_print_info(Xive2End * end,uint32_t width,GString * buf)214 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf)
215 {
216 uint64_t qaddr_base = xive2_end_qaddr(end);
217 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
218 uint32_t qentries = xive2_end_get_qentries(end);
219 int i;
220
221 /*
222 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
223 */
224 g_string_append_printf(buf, " [ ");
225 qindex = (qindex - (width - 1)) & (qentries - 1);
226 for (i = 0; i < width; i++) {
227 uint64_t qaddr = qaddr_base + (qindex << 2);
228 uint32_t qdata = -1;
229
230 if (dma_memory_read(&address_space_memory, qaddr, &qdata,
231 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) {
232 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%"
233 HWADDR_PRIx "\n", qaddr);
234 return;
235 }
236 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "",
237 be32_to_cpu(qdata));
238 qindex = (qindex + 1) & (qentries - 1);
239 }
240 g_string_append_printf(buf, "]");
241 }
242
xive2_end_pic_print_info(Xive2End * end,uint32_t end_idx,GString * buf)243 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf)
244 {
245 uint64_t qaddr_base = xive2_end_qaddr(end);
246 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
247 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
248 uint32_t qentries = xive2_end_get_qentries(end);
249
250 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6);
251 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6);
252 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7);
253 uint8_t pq;
254
255 if (!xive2_end_is_valid(end)) {
256 return;
257 }
258
259 pq = xive_get_field32(END2_W1_ESn, end->w1);
260
261 g_string_append_printf(buf,
262 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c "
263 "prio:%d nvp:%02x/%04x",
264 end_idx,
265 pq & XIVE_ESB_VAL_P ? 'P' : '-',
266 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
267 xive2_end_is_valid(end) ? 'v' : '-',
268 xive2_end_is_enqueue(end) ? 'q' : '-',
269 xive2_end_is_notify(end) ? 'n' : '-',
270 xive2_end_is_backlog(end) ? 'b' : '-',
271 xive2_end_is_precluded_escalation(end) ? 'p' : '-',
272 xive2_end_is_escalate(end) ? 'e' : '-',
273 xive2_end_is_escalate_end(end) ? 'N' : '-',
274 xive2_end_is_uncond_escalation(end) ? 'u' : '-',
275 xive2_end_is_silent_escalation(end) ? 's' : '-',
276 xive2_end_is_firmware1(end) ? 'f' : '-',
277 xive2_end_is_firmware2(end) ? 'F' : '-',
278 xive2_end_is_ignore(end) ? 'i' : '-',
279 xive2_end_is_crowd(end) ? 'c' : '-',
280 priority, nvx_blk, nvx_idx);
281
282 if (qaddr_base) {
283 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d",
284 qaddr_base, qindex, qentries, qgen);
285 xive2_end_queue_pic_print_info(end, 6, buf);
286 }
287 g_string_append_c(buf, '\n');
288 }
289
xive2_end_eas_pic_print_info(Xive2End * end,uint32_t end_idx,GString * buf)290 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
291 GString *buf)
292 {
293 Xive2Eas *eas = (Xive2Eas *) &end->w4;
294 uint8_t pq;
295
296 if (!xive2_end_is_escalate(end)) {
297 return;
298 }
299
300 pq = xive_get_field32(END2_W1_ESe, end->w1);
301
302 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
303 end_idx,
304 pq & XIVE_ESB_VAL_P ? 'P' : '-',
305 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
306 xive2_eas_is_valid(eas) ? 'v' : ' ',
307 xive2_eas_is_masked(eas) ? 'M' : ' ',
308 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
309 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
310 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
311 }
312
xive2_nvp_pic_print_info(Xive2Nvp * nvp,uint32_t nvp_idx,GString * buf)313 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf)
314 {
315 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
316 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
317 uint64_t cache_line = xive2_nvp_reporting_addr(nvp);
318
319 if (!xive2_nvp_is_valid(nvp)) {
320 return;
321 }
322
323 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x",
324 nvp_idx, eq_blk, eq_idx,
325 xive_get_field32(NVP2_W2_IPB, nvp->w2),
326 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0));
327 if (cache_line) {
328 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line);
329 }
330
331 /*
332 * When the NVP is HW controlled, more fields are updated
333 */
334 if (xive2_nvp_is_hw(nvp)) {
335 g_string_append_printf(buf, " CPPR:%02x",
336 xive_get_field32(NVP2_W2_CPPR, nvp->w2));
337 if (xive2_nvp_is_co(nvp)) {
338 g_string_append_printf(buf, " CO:%04x",
339 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));
340 }
341 }
342 g_string_append_c(buf, '\n');
343 }
344
xive2_nvgc_pic_print_info(Xive2Nvgc * nvgc,uint32_t nvgc_idx,GString * buf)345 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf)
346 {
347 uint8_t i;
348
349 if (!xive2_nvgc_is_valid(nvgc)) {
350 return;
351 }
352
353 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx,
354 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0));
355 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) {
356 g_string_append_printf(buf, "[%d]=0x%x ",
357 i, xive2_nvgc_get_backlog(nvgc, i));
358 }
359 g_string_append_printf(buf, "\n");
360 }
361
xive2_end_enqueue(Xive2End * end,uint32_t data)362 static void xive2_end_enqueue(Xive2End *end, uint32_t data)
363 {
364 uint64_t qaddr_base = xive2_end_qaddr(end);
365 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
366 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
367
368 uint64_t qaddr = qaddr_base + (qindex << 2);
369 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));
370 uint32_t qentries = xive2_end_get_qentries(end);
371
372 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata),
373 MEMTXATTRS_UNSPECIFIED)) {
374 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%"
375 HWADDR_PRIx "\n", qaddr);
376 return;
377 }
378
379 qindex = (qindex + 1) & (qentries - 1);
380 if (qindex == 0) {
381 qgen ^= 1;
382 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen);
383
384 /* Set gen flipped to 1, it gets reset on a cache watch operation */
385 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1);
386 }
387 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
388 }
389
xive2_pgofnext(uint8_t * nvgc_blk,uint32_t * nvgc_idx,uint8_t next_level)390 static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx,
391 uint8_t next_level)
392 {
393 uint32_t mask, next_idx;
394 uint8_t next_blk;
395
396 /*
397 * Adjust the block and index of a VP for the next group/crowd
398 * size (PGofFirst/PGofNext field in the NVP and NVGC structures).
399 *
400 * The 6-bit group level is split into a 2-bit crowd and 4-bit
401 * group levels. Encoding is similar. However, we don't support
402 * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd
403 * size of 16.
404 */
405 next_blk = NVx_CROWD_LVL(next_level);
406 if (next_blk == 3) {
407 next_blk = 4;
408 }
409 mask = (1 << next_blk) - 1;
410 *nvgc_blk &= ~mask;
411 *nvgc_blk |= mask >> 1;
412
413 next_idx = NVx_GROUP_LVL(next_level);
414 mask = (1 << next_idx) - 1;
415 *nvgc_idx &= ~mask;
416 *nvgc_idx |= mask >> 1;
417 }
418
419 /*
420 * Scan the group chain and return the highest priority and group
421 * level of pending group interrupts.
422 */
xive2_presenter_backlog_scan(XivePresenter * xptr,uint8_t nvx_blk,uint32_t nvx_idx,uint8_t first_group,uint8_t * out_level)423 static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr,
424 uint8_t nvx_blk, uint32_t nvx_idx,
425 uint8_t first_group,
426 uint8_t *out_level)
427 {
428 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
429 uint32_t nvgc_idx;
430 uint32_t current_level, count;
431 uint8_t nvgc_blk, prio;
432 Xive2Nvgc nvgc;
433
434 for (prio = 0; prio <= XIVE_PRIORITY_MAX; prio++) {
435 current_level = first_group & 0x3F;
436 nvgc_blk = nvx_blk;
437 nvgc_idx = nvx_idx;
438
439 while (current_level) {
440 xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level);
441
442 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level),
443 nvgc_blk, nvgc_idx, &nvgc)) {
444 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n",
445 nvgc_blk, nvgc_idx);
446 return 0xFF;
447 }
448 if (!xive2_nvgc_is_valid(&nvgc)) {
449 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n",
450 nvgc_blk, nvgc_idx);
451 return 0xFF;
452 }
453
454 count = xive2_nvgc_get_backlog(&nvgc, prio);
455 if (count) {
456 *out_level = current_level;
457 return prio;
458 }
459 current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F;
460 }
461 }
462 return 0xFF;
463 }
464
xive2_presenter_backlog_decr(XivePresenter * xptr,uint8_t nvx_blk,uint32_t nvx_idx,uint8_t group_prio,uint8_t group_level)465 static void xive2_presenter_backlog_decr(XivePresenter *xptr,
466 uint8_t nvx_blk, uint32_t nvx_idx,
467 uint8_t group_prio,
468 uint8_t group_level)
469 {
470 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
471 uint32_t nvgc_idx, count;
472 uint8_t nvgc_blk;
473 Xive2Nvgc nvgc;
474
475 nvgc_blk = nvx_blk;
476 nvgc_idx = nvx_idx;
477 xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level);
478
479 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level),
480 nvgc_blk, nvgc_idx, &nvgc)) {
481 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n",
482 nvgc_blk, nvgc_idx);
483 return;
484 }
485 if (!xive2_nvgc_is_valid(&nvgc)) {
486 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n",
487 nvgc_blk, nvgc_idx);
488 return;
489 }
490 count = xive2_nvgc_get_backlog(&nvgc, group_prio);
491 if (!count) {
492 return;
493 }
494 xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1);
495 xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level),
496 nvgc_blk, nvgc_idx, &nvgc);
497 }
498
499 /*
500 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
501 *
502 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit
503 *
504 * - if a context is enabled with the H bit set, the VP context
505 * information is retrieved from the NVP structure (“check out”)
506 * and stored back on a context pull (“check in”), the SW receives
507 * the same context pull information as on P9
508 *
509 * - the H bit cannot be changed while the V bit is set, i.e. a
510 * context cannot be set up in the TIMA and then be “pushed” into
511 * the NVP by changing the H bit while the context is enabled
512 */
513
xive2_tctx_save_ctx(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t ring,uint8_t nvp_blk,uint32_t nvp_idx)514 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
515 uint8_t ring,
516 uint8_t nvp_blk, uint32_t nvp_idx)
517 {
518 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
519 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
520 Xive2Nvp nvp;
521 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
522 uint8_t *regs = &tctx->regs[ring];
523
524 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
525 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
526 nvp_blk, nvp_idx);
527 return;
528 }
529
530 if (!xive2_nvp_is_valid(&nvp)) {
531 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
532 nvp_blk, nvp_idx);
533 return;
534 }
535
536 if (!xive2_nvp_is_hw(&nvp)) {
537 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
538 nvp_blk, nvp_idx);
539 return;
540 }
541
542 if (!xive2_nvp_is_co(&nvp)) {
543 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n",
544 nvp_blk, nvp_idx);
545 return;
546 }
547
548 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) &&
549 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) {
550 qemu_log_mask(LOG_GUEST_ERROR,
551 "XIVE: NVP %x/%x invalid checkout Thread %x\n",
552 nvp_blk, nvp_idx, pir);
553 return;
554 }
555
556 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
557
558 if ((nvp.w0 & NVP2_W0_P) || ring != TM_QW2_HV_POOL) {
559 /*
560 * Non-pool contexts always save CPPR (ignore p bit). XXX: Clarify
561 * whether that is the correct behaviour.
562 */
563 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, sig_regs[TM_CPPR]);
564 }
565 if (nvp.w0 & NVP2_W0_L) {
566 /*
567 * Typically not used. If LSMFB is restored with 0, it will
568 * force a backlog rescan
569 */
570 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
571 }
572 if (nvp.w0 & NVP2_W0_G) {
573 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]);
574 }
575 if (nvp.w0 & NVP2_W0_T) {
576 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]);
577 }
578 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
579
580 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
581 /* NVP2_W1_CO_THRID_VALID only set once */
582 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF);
583 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);
584 }
585
586 /* POOL cam is the same as OS cam encoding */
xive2_cam_decode(uint32_t cam,uint8_t * nvp_blk,uint32_t * nvp_idx,bool * valid,bool * hw)587 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk,
588 uint32_t *nvp_idx, bool *valid, bool *hw)
589 {
590 *nvp_blk = xive2_nvp_blk(cam);
591 *nvp_idx = xive2_nvp_idx(cam);
592 *valid = !!(cam & TM2_W2_VALID);
593 *hw = !!(cam & TM2_W2_HW);
594 }
595
596 /*
597 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id
598 * width and block id width is configurable at the IC level.
599 *
600 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit)
601 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit)
602 */
xive2_tctx_hw_cam_line(XivePresenter * xptr,XiveTCTX * tctx)603 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
604 {
605 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
606 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
607 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
608 uint8_t blk = xive2_router_get_block_id(xrtr);
609 uint8_t tid_shift =
610 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7;
611 uint8_t tid_mask = (1 << tid_shift) - 1;
612
613 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));
614 }
615
xive2_redistribute(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t ring)616 static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring)
617 {
618 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
619 uint8_t nsr = sig_regs[TM_NSR];
620 uint8_t pipr = sig_regs[TM_PIPR];
621 uint8_t crowd = NVx_CROWD_LVL(nsr);
622 uint8_t group = NVx_GROUP_LVL(nsr);
623 uint8_t nvgc_blk, end_blk, nvp_blk;
624 uint32_t nvgc_idx, end_idx, nvp_idx;
625 Xive2Nvgc nvgc;
626 uint8_t prio_limit;
627 uint32_t cfg;
628
629 /* redistribution is only for group/crowd interrupts */
630 if (!xive_nsr_indicates_group_exception(ring, nsr)) {
631 return;
632 }
633
634 /* Don't check return code since ring is expected to be invalidated */
635 xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx);
636
637 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx);
638
639 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx);
640 /* convert crowd/group to blk/idx */
641 if (group > 0) {
642 nvgc_idx = (nvp_idx & (0xffffffff << group)) |
643 ((1 << (group - 1)) - 1);
644 } else {
645 nvgc_idx = nvp_idx;
646 }
647
648 if (crowd > 0) {
649 crowd = (crowd == 3) ? 4 : crowd;
650 nvgc_blk = (nvp_blk & (0xffffffff << crowd)) |
651 ((1 << (crowd - 1)) - 1);
652 } else {
653 nvgc_blk = nvp_blk;
654 }
655
656 /* Use blk/idx to retrieve the NVGC */
657 if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) {
658 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n",
659 crowd ? "NVC" : "NVG", nvgc_blk, nvgc_idx);
660 return;
661 }
662
663 /* retrieve the END blk/idx from the NVGC */
664 end_blk = xive_get_field32(NVGC2_W1_END_BLK, nvgc.w1);
665 end_idx = xive_get_field32(NVGC2_W1_END_IDX, nvgc.w1);
666
667 /* determine number of priorities being used */
668 cfg = xive2_router_get_config(xrtr);
669 if (cfg & XIVE2_EN_VP_GRP_PRIORITY) {
670 prio_limit = 1 << GETFIELD(NVGC2_W1_PSIZE, nvgc.w1);
671 } else {
672 prio_limit = 1 << GETFIELD(XIVE2_VP_INT_PRIO, cfg);
673 }
674
675 /* add priority offset to end index */
676 end_idx += pipr % prio_limit;
677
678 /* trigger the group END */
679 xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true);
680
681 /* clear interrupt indication for the context */
682 sig_regs[TM_NSR] = 0;
683 sig_regs[TM_PIPR] = sig_regs[TM_CPPR];
684 xive_tctx_reset_signal(tctx, ring);
685 }
686
687 static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring);
688
xive2_tm_pull_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,unsigned size,uint8_t ring)689 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx,
690 hwaddr offset, unsigned size, uint8_t ring)
691 {
692 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
693 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]);
694 uint32_t cam = be32_to_cpu(target_ringw2);
695 uint8_t nvp_blk;
696 uint32_t nvp_idx;
697 uint8_t cur_ring;
698 bool valid;
699 bool do_save;
700 uint8_t nsr;
701
702 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save);
703
704 if (xive2_tctx_get_nvp_indexes(tctx, ring, &nvp_blk, &nvp_idx)) {
705 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
706 nvp_blk, nvp_idx);
707 }
708
709 /* Invalidate CAM line of requested ring and all lower rings */
710 for (cur_ring = TM_QW0_USER; cur_ring <= ring;
711 cur_ring += XIVE_TM_RING_SIZE) {
712 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]);
713 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0);
714 bool is_valid = !!(xive_get_field32(TM2_QW1W2_VO, ringw2));
715 uint8_t *sig_regs;
716
717 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4);
718
719 /* Skip the rest for USER or invalid contexts */
720 if ((cur_ring == TM_QW0_USER) || !is_valid) {
721 continue;
722 }
723
724 /* Active group/crowd interrupts need to be redistributed */
725 sig_regs = xive_tctx_signal_regs(tctx, ring);
726 nsr = sig_regs[TM_NSR];
727 if (xive_nsr_indicates_group_exception(cur_ring, nsr)) {
728 /* Ensure ring matches NSR (for HV NSR POOL vs PHYS rings) */
729 if (cur_ring == xive_nsr_exception_ring(cur_ring, nsr)) {
730 xive2_redistribute(xrtr, tctx, cur_ring);
731 }
732 }
733
734 /*
735 * Lower external interrupt line of requested ring and below except for
736 * USER, which doesn't exist.
737 */
738 if (xive_nsr_indicates_exception(cur_ring, nsr)) {
739 if (cur_ring == xive_nsr_exception_ring(cur_ring, nsr)) {
740 xive_tctx_reset_signal(tctx, cur_ring);
741 }
742 }
743 }
744
745 if (ring == TM_QW2_HV_POOL) {
746 /* Re-check phys for interrupts if pool was disabled */
747 nsr = tctx->regs[TM_QW3_HV_PHYS + TM_NSR];
748 if (xive_nsr_indicates_exception(TM_QW3_HV_PHYS, nsr)) {
749 /* Ring must be PHYS because POOL would have been redistributed */
750 g_assert(xive_nsr_exception_ring(TM_QW3_HV_PHYS, nsr) ==
751 TM_QW3_HV_PHYS);
752 } else {
753 xive2_tctx_process_pending(tctx, TM_QW3_HV_PHYS);
754 }
755 }
756
757 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {
758 xive2_tctx_save_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx);
759 }
760
761 return target_ringw2;
762 }
763
xive2_tm_pull_os_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,unsigned size)764 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
765 hwaddr offset, unsigned size)
766 {
767 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS);
768 }
769
xive2_tm_pull_pool_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,unsigned size)770 uint64_t xive2_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
771 hwaddr offset, unsigned size)
772 {
773 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW2_HV_POOL);
774 }
775
xive2_tm_pull_phys_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,unsigned size)776 uint64_t xive2_tm_pull_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx,
777 hwaddr offset, unsigned size)
778 {
779 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW3_HV_PHYS);
780 }
781
782 #define REPORT_LINE_GEN1_SIZE 16
783
xive2_tm_report_line_gen1(XiveTCTX * tctx,uint8_t * data,uint8_t size)784 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data,
785 uint8_t size)
786 {
787 uint8_t *regs = tctx->regs;
788
789 g_assert(size == REPORT_LINE_GEN1_SIZE);
790 memset(data, 0, size);
791 /*
792 * See xive architecture for description of what is saved. It is
793 * hand-picked information to fit in 16 bytes.
794 */
795 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR];
796 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR];
797 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB];
798 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB];
799 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT];
800 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS];
801 data[0x6] = 0xFF;
802 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80;
803 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1;
804 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2;
805 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3);
806 data[0x8] = regs[TM_QW1_OS + TM_NSR];
807 data[0x9] = regs[TM_QW1_OS + TM_CPPR];
808 data[0xA] = regs[TM_QW1_OS + TM_IPB];
809 data[0xB] = regs[TM_QW1_OS + TM_LGS];
810 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) {
811 /*
812 * Logical server extension, except VU bit replaced by EB bit
813 * from NSR
814 */
815 data[0xC] = regs[TM_QW0_USER + TM_WORD2];
816 data[0xC] &= ~0x80;
817 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80;
818 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1];
819 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2];
820 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3];
821 }
822 }
823
xive2_tm_pull_ctx_ol(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size,uint8_t ring)824 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
825 hwaddr offset, uint64_t value,
826 unsigned size, uint8_t ring)
827 {
828 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
829 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved;
830 uint8_t nvp_blk;
831 Xive2Nvp nvp;
832 uint64_t phys_addr;
833 MemTxResult result;
834
835 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx);
836 nvp_blk = xive2_nvp_blk(hw_cam);
837 nvp_idx = xive2_nvp_idx(hw_cam);
838
839 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
840 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
841 nvp_blk, nvp_idx);
842 return;
843 }
844
845 if (!xive2_nvp_is_valid(&nvp)) {
846 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
847 nvp_blk, nvp_idx);
848 return;
849 }
850
851 xive2_cfg = xive2_router_get_config(xrtr);
852
853 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */
854 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) {
855 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE];
856
857 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE);
858 result = dma_memory_write(&address_space_memory, phys_addr,
859 pull_ctxt, REPORT_LINE_GEN1_SIZE,
860 MEMTXATTRS_UNSPECIFIED);
861 assert(result == MEMTX_OK);
862 } else {
863 result = dma_memory_write(&address_space_memory, phys_addr,
864 &tctx->regs, sizeof(tctx->regs),
865 MEMTXATTRS_UNSPECIFIED);
866 assert(result == MEMTX_OK);
867 reserved = 0xFFFFFFFF;
868 result = dma_memory_write(&address_space_memory, phys_addr + 12,
869 &reserved, sizeof(reserved),
870 MEMTXATTRS_UNSPECIFIED);
871 assert(result == MEMTX_OK);
872 }
873
874 /* the rest is similar to pull context to registers */
875 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring);
876 }
877
xive2_tm_pull_os_ctx_ol(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)878 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
879 hwaddr offset, uint64_t value, unsigned size)
880 {
881 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS);
882 }
883
884
xive2_tm_pull_phys_ctx_ol(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)885 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
886 hwaddr offset, uint64_t value, unsigned size)
887 {
888 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS);
889 }
890
xive2_tctx_restore_ctx(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t ring,uint8_t nvp_blk,uint32_t nvp_idx,Xive2Nvp * nvp)891 static uint8_t xive2_tctx_restore_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
892 uint8_t ring,
893 uint8_t nvp_blk, uint32_t nvp_idx,
894 Xive2Nvp *nvp)
895 {
896 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
897 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
898 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
899 uint8_t *regs = &tctx->regs[ring];
900 uint8_t cppr;
901
902 if (!xive2_nvp_is_hw(nvp)) {
903 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
904 nvp_blk, nvp_idx);
905 return 0;
906 }
907
908 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2);
909 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0);
910 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
911
912 sig_regs[TM_CPPR] = cppr;
913 regs[TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2);
914 regs[TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2);
915 regs[TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2);
916
917 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
918 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);
919 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir);
920
921 /*
922 * Checkout privilege: 0:OS, 1:Pool, 2:Hard
923 *
924 * TODO: we don't support hard push/pull
925 */
926 switch (ring) {
927 case TM_QW1_OS:
928 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0);
929 break;
930 case TM_QW2_HV_POOL:
931 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 1);
932 break;
933 default:
934 g_assert_not_reached();
935 }
936
937 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1);
938
939 /* return restored CPPR to generate a CPU exception if needed */
940 return cppr;
941 }
942
943 /* Restore TIMA VP context from NVP backlog */
xive2_tctx_restore_nvp(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t ring,uint8_t nvp_blk,uint32_t nvp_idx,bool do_restore)944 static void xive2_tctx_restore_nvp(Xive2Router *xrtr, XiveTCTX *tctx,
945 uint8_t ring,
946 uint8_t nvp_blk, uint32_t nvp_idx,
947 bool do_restore)
948 {
949 uint8_t *regs = &tctx->regs[ring];
950 uint8_t ipb;
951 Xive2Nvp nvp;
952
953 /*
954 * Grab the associated thread interrupt context registers in the
955 * associated NVP
956 */
957 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
958 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
959 nvp_blk, nvp_idx);
960 return;
961 }
962
963 if (!xive2_nvp_is_valid(&nvp)) {
964 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
965 nvp_blk, nvp_idx);
966 return;
967 }
968
969 /* Automatically restore thread context registers */
970 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_restore) {
971 xive2_tctx_restore_ctx(xrtr, tctx, ring, nvp_blk, nvp_idx, &nvp);
972 }
973
974 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
975 if (ipb) {
976 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
977 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
978 }
979 /* IPB bits in the backlog are merged with the TIMA IPB bits */
980 regs[TM_IPB] |= ipb;
981 }
982
983 /*
984 * Updating the ring CAM line can trigger a resend of interrupt
985 */
xive2_tm_push_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size,uint8_t ring)986 static void xive2_tm_push_ctx(XivePresenter *xptr, XiveTCTX *tctx,
987 hwaddr offset, uint64_t value, unsigned size,
988 uint8_t ring)
989 {
990 uint32_t cam;
991 uint32_t w2;
992 uint64_t dw1;
993 uint8_t nvp_blk;
994 uint32_t nvp_idx;
995 bool v;
996 bool do_restore;
997
998 if (xive_ring_valid(tctx, ring)) {
999 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Attempt to push VP to enabled"
1000 " ring 0x%02x\n", ring);
1001 return;
1002 }
1003
1004 /* First update the thead context */
1005 switch (size) {
1006 case 1:
1007 tctx->regs[ring + TM_WORD2] = value & 0xff;
1008 cam = xive2_tctx_hw_cam_line(xptr, tctx);
1009 cam |= ((value & 0xc0) << 24); /* V and H bits */
1010 break;
1011 case 4:
1012 cam = value;
1013 w2 = cpu_to_be32(cam);
1014 memcpy(&tctx->regs[ring + TM_WORD2], &w2, 4);
1015 break;
1016 case 8:
1017 cam = value >> 32;
1018 dw1 = cpu_to_be64(value);
1019 memcpy(&tctx->regs[ring + TM_WORD2], &dw1, 8);
1020 break;
1021 default:
1022 g_assert_not_reached();
1023 }
1024
1025 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &v, &do_restore);
1026
1027 /* Check the interrupt pending bits */
1028 if (v) {
1029 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
1030 uint8_t cur_ring;
1031
1032 xive2_tctx_restore_nvp(xrtr, tctx, ring,
1033 nvp_blk, nvp_idx, do_restore);
1034
1035 for (cur_ring = TM_QW1_OS; cur_ring <= ring;
1036 cur_ring += XIVE_TM_RING_SIZE) {
1037 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, cur_ring);
1038 uint8_t nsr = sig_regs[TM_NSR];
1039
1040 if (!xive_ring_valid(tctx, cur_ring)) {
1041 continue;
1042 }
1043
1044 if (cur_ring == TM_QW2_HV_POOL) {
1045 if (xive_nsr_indicates_exception(cur_ring, nsr)) {
1046 g_assert(xive_nsr_exception_ring(cur_ring, nsr) ==
1047 TM_QW3_HV_PHYS);
1048 xive2_redistribute(xrtr, tctx,
1049 xive_nsr_exception_ring(ring, nsr));
1050 }
1051 xive2_tctx_process_pending(tctx, TM_QW3_HV_PHYS);
1052 break;
1053 }
1054 xive2_tctx_process_pending(tctx, cur_ring);
1055 }
1056 }
1057 }
1058
xive2_tm_push_os_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1059 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
1060 hwaddr offset, uint64_t value, unsigned size)
1061 {
1062 xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW1_OS);
1063 }
1064
xive2_tm_push_pool_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1065 void xive2_tm_push_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
1066 hwaddr offset, uint64_t value, unsigned size)
1067 {
1068 xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW2_HV_POOL);
1069 }
1070
xive2_tm_push_phys_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1071 void xive2_tm_push_phys_ctx(XivePresenter *xptr, XiveTCTX *tctx,
1072 hwaddr offset, uint64_t value, unsigned size)
1073 {
1074 xive2_tm_push_ctx(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS);
1075 }
1076
1077 /* returns -1 if ring is invalid, but still populates block and index */
xive2_tctx_get_nvp_indexes(XiveTCTX * tctx,uint8_t ring,uint8_t * nvp_blk,uint32_t * nvp_idx)1078 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring,
1079 uint8_t *nvp_blk, uint32_t *nvp_idx)
1080 {
1081 uint32_t w2;
1082 uint32_t cam = 0;
1083 int rc = 0;
1084
1085 w2 = xive_tctx_word2(&tctx->regs[ring]);
1086 switch (ring) {
1087 case TM_QW1_OS:
1088 if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) {
1089 rc = -1;
1090 }
1091 cam = xive_get_field32(TM2_QW1W2_OS_CAM, w2);
1092 break;
1093 case TM_QW2_HV_POOL:
1094 if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) {
1095 rc = -1;
1096 }
1097 cam = xive_get_field32(TM2_QW2W2_POOL_CAM, w2);
1098 break;
1099 case TM_QW3_HV_PHYS:
1100 if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) {
1101 rc = -1;
1102 }
1103 cam = xive2_tctx_hw_cam_line(tctx->xptr, tctx);
1104 break;
1105 default:
1106 rc = -1;
1107 }
1108 *nvp_blk = xive2_nvp_blk(cam);
1109 *nvp_idx = xive2_nvp_idx(cam);
1110 return rc;
1111 }
1112
xive2_tctx_accept_el(XivePresenter * xptr,XiveTCTX * tctx,uint8_t ring,uint8_t cl_ring)1113 static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx,
1114 uint8_t ring, uint8_t cl_ring)
1115 {
1116 uint64_t rd;
1117 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
1118 uint32_t nvp_idx, xive2_cfg;
1119 uint8_t nvp_blk;
1120 Xive2Nvp nvp;
1121 uint64_t phys_addr;
1122 uint8_t OGen = 0;
1123
1124 xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx);
1125
1126 if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) {
1127 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
1128 nvp_blk, nvp_idx);
1129 return;
1130 }
1131
1132 if (!xive2_nvp_is_valid(&nvp)) {
1133 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
1134 nvp_blk, nvp_idx);
1135 return;
1136 }
1137
1138
1139 rd = xive_tctx_accept(tctx, ring);
1140
1141 if (ring == TM_QW1_OS) {
1142 OGen = tctx->regs[ring + TM_OGEN];
1143 }
1144 xive2_cfg = xive2_router_get_config(xrtr);
1145 phys_addr = xive2_nvp_reporting_addr(&nvp);
1146 uint8_t report_data[REPORT_LINE_GEN1_SIZE];
1147 memset(report_data, 0xff, sizeof(report_data));
1148 if ((OGen == 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) {
1149 report_data[8] = (rd >> 8) & 0xff;
1150 report_data[9] = rd & 0xff;
1151 } else {
1152 report_data[0] = (rd >> 8) & 0xff;
1153 report_data[1] = rd & 0xff;
1154 }
1155 cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZE);
1156 }
1157
xive2_tm_ack_os_el(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1158 void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx,
1159 hwaddr offset, uint64_t value, unsigned size)
1160 {
1161 xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS);
1162 }
1163
1164 /* Re-calculate and present pending interrupts */
xive2_tctx_process_pending(XiveTCTX * tctx,uint8_t sig_ring)1165 static void xive2_tctx_process_pending(XiveTCTX *tctx, uint8_t sig_ring)
1166 {
1167 uint8_t *sig_regs = &tctx->regs[sig_ring];
1168 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr);
1169 uint8_t backlog_prio;
1170 uint8_t first_group;
1171 uint8_t group_level;
1172 uint8_t pipr_min;
1173 uint8_t lsmfb_min;
1174 uint8_t ring_min;
1175 uint8_t cppr = sig_regs[TM_CPPR];
1176 bool group_enabled;
1177 Xive2Nvp nvp;
1178 int rc;
1179
1180 g_assert(sig_ring == TM_QW3_HV_PHYS || sig_ring == TM_QW1_OS);
1181 g_assert(sig_regs[TM_WORD2] & 0x80);
1182 g_assert(!xive_nsr_indicates_group_exception(sig_ring, sig_regs[TM_NSR]));
1183
1184 /*
1185 * Recompute the PIPR based on local pending interrupts. It will
1186 * be adjusted below if needed in case of pending group interrupts.
1187 */
1188 again:
1189 pipr_min = xive_ipb_to_pipr(sig_regs[TM_IPB]);
1190 group_enabled = !!sig_regs[TM_LGS];
1191 lsmfb_min = group_enabled ? sig_regs[TM_LSMFB] : 0xff;
1192 ring_min = sig_ring;
1193 group_level = 0;
1194
1195 /* PHYS updates also depend on POOL values */
1196 if (sig_ring == TM_QW3_HV_PHYS) {
1197 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL];
1198
1199 /* POOL values only matter if POOL ctx is valid */
1200 if (pool_regs[TM_WORD2] & 0x80) {
1201 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]);
1202 uint8_t pool_lsmfb = pool_regs[TM_LSMFB];
1203
1204 /*
1205 * Determine highest priority interrupt and
1206 * remember which ring has it.
1207 */
1208 if (pool_pipr < pipr_min) {
1209 pipr_min = pool_pipr;
1210 if (pool_pipr < lsmfb_min) {
1211 ring_min = TM_QW2_HV_POOL;
1212 }
1213 }
1214
1215 /* Values needed for group priority calculation */
1216 if (pool_regs[TM_LGS] && (pool_lsmfb < lsmfb_min)) {
1217 group_enabled = true;
1218 lsmfb_min = pool_lsmfb;
1219 if (lsmfb_min < pipr_min) {
1220 ring_min = TM_QW2_HV_POOL;
1221 }
1222 }
1223 }
1224 }
1225
1226 if (group_enabled &&
1227 lsmfb_min < cppr &&
1228 lsmfb_min < pipr_min) {
1229
1230 uint8_t nvp_blk;
1231 uint32_t nvp_idx;
1232
1233 /*
1234 * Thread has seen a group interrupt with a higher priority
1235 * than the new cppr or pending local interrupt. Check the
1236 * backlog
1237 */
1238 rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx);
1239 if (rc) {
1240 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid "
1241 "context\n");
1242 return;
1243 }
1244
1245 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
1246 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
1247 nvp_blk, nvp_idx);
1248 return;
1249 }
1250
1251 if (!xive2_nvp_is_valid(&nvp)) {
1252 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
1253 nvp_blk, nvp_idx);
1254 return;
1255 }
1256
1257 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0);
1258 if (!first_group) {
1259 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
1260 nvp_blk, nvp_idx);
1261 return;
1262 }
1263
1264 backlog_prio = xive2_presenter_backlog_scan(tctx->xptr,
1265 nvp_blk, nvp_idx,
1266 first_group, &group_level);
1267 tctx->regs[ring_min + TM_LSMFB] = backlog_prio;
1268 if (backlog_prio != lsmfb_min) {
1269 /*
1270 * If the group backlog scan finds a less favored or no interrupt,
1271 * then re-do the processing which may turn up a more favored
1272 * interrupt from IPB or the other pool. Backlog should not
1273 * find a priority < LSMFB.
1274 */
1275 g_assert(backlog_prio >= lsmfb_min);
1276 goto again;
1277 }
1278
1279 xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx,
1280 backlog_prio, group_level);
1281 pipr_min = backlog_prio;
1282 }
1283
1284 if (pipr_min > cppr) {
1285 pipr_min = cppr;
1286 }
1287 xive_tctx_pipr_set(tctx, ring_min, pipr_min, group_level);
1288 }
1289
1290 /* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */
xive2_tctx_set_cppr(XiveTCTX * tctx,uint8_t sig_ring,uint8_t cppr)1291 static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t sig_ring, uint8_t cppr)
1292 {
1293 uint8_t *sig_regs = &tctx->regs[sig_ring];
1294 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr);
1295 uint8_t old_cppr;
1296 uint8_t nsr = sig_regs[TM_NSR];
1297
1298 g_assert(sig_ring == TM_QW1_OS || sig_ring == TM_QW3_HV_PHYS);
1299
1300 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_NSR] == 0);
1301 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0);
1302 g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0);
1303
1304 /* XXX: should show pool IPB for PHYS ring */
1305 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, sig_ring,
1306 sig_regs[TM_IPB], sig_regs[TM_PIPR],
1307 cppr, nsr);
1308
1309 if (cppr > XIVE_PRIORITY_MAX) {
1310 cppr = 0xff;
1311 }
1312
1313 old_cppr = sig_regs[TM_CPPR];
1314 sig_regs[TM_CPPR] = cppr;
1315
1316 /* Handle increased CPPR priority (lower value) */
1317 if (cppr < old_cppr) {
1318 if (cppr <= sig_regs[TM_PIPR]) {
1319 /* CPPR lowered below PIPR, must un-present interrupt */
1320 if (xive_nsr_indicates_exception(sig_ring, nsr)) {
1321 if (xive_nsr_indicates_group_exception(sig_ring, nsr)) {
1322 /* redistribute precluded active grp interrupt */
1323 xive2_redistribute(xrtr, tctx,
1324 xive_nsr_exception_ring(sig_ring, nsr));
1325 return;
1326 }
1327 }
1328
1329 /* interrupt is VP directed, pending in IPB */
1330 xive_tctx_pipr_set(tctx, sig_ring, cppr, 0);
1331 return;
1332 } else {
1333 /* CPPR was lowered, but still above PIPR. No action needed. */
1334 return;
1335 }
1336 }
1337
1338 /* CPPR didn't change, nothing needs to be done */
1339 if (cppr == old_cppr) {
1340 return;
1341 }
1342
1343 /* CPPR priority decreased (higher value) */
1344 if (!xive_nsr_indicates_exception(sig_ring, nsr)) {
1345 xive2_tctx_process_pending(tctx, sig_ring);
1346 }
1347 }
1348
xive2_tm_set_hv_cppr(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1349 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
1350 hwaddr offset, uint64_t value, unsigned size)
1351 {
1352 xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
1353 }
1354
xive2_tm_set_os_cppr(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1355 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
1356 hwaddr offset, uint64_t value, unsigned size)
1357 {
1358 xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
1359 }
1360
1361 /*
1362 * Adjust the IPB to allow a CPU to process event queues of other
1363 * priorities during one physical interrupt cycle.
1364 */
xive2_tm_set_os_pending(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1365 void xive2_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
1366 hwaddr offset, uint64_t value, unsigned size)
1367 {
1368 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
1369 uint8_t ring = TM_QW1_OS;
1370 uint8_t *regs = &tctx->regs[ring];
1371 uint8_t priority = value & 0xff;
1372
1373 /*
1374 * XXX: should this simply set a bit in IPB and wait for it to be picked
1375 * up next cycle, or is it supposed to present it now? We implement the
1376 * latter here.
1377 */
1378 regs[TM_IPB] |= xive_priority_to_ipb(priority);
1379 if (xive_ipb_to_pipr(regs[TM_IPB]) >= regs[TM_PIPR]) {
1380 return;
1381 }
1382 if (xive_nsr_indicates_group_exception(ring, regs[TM_NSR])) {
1383 xive2_redistribute(xrtr, tctx, ring);
1384 }
1385
1386 xive_tctx_pipr_present(tctx, ring, priority, 0);
1387 }
1388
xive2_tctx_set_target(XiveTCTX * tctx,uint8_t ring,uint8_t target)1389 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target)
1390 {
1391 uint8_t *regs = &tctx->regs[ring];
1392
1393 regs[TM_T] = target;
1394 }
1395
xive2_tm_set_hv_target(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)1396 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
1397 hwaddr offset, uint64_t value, unsigned size)
1398 {
1399 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff);
1400 }
1401
1402 /*
1403 * XIVE Router (aka. Virtualization Controller or IVRE)
1404 */
1405
xive2_router_get_eas(Xive2Router * xrtr,uint8_t eas_blk,uint32_t eas_idx,Xive2Eas * eas)1406 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
1407 Xive2Eas *eas)
1408 {
1409 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1410
1411 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
1412 }
1413
1414 static
xive2_router_get_pq(Xive2Router * xrtr,uint8_t eas_blk,uint32_t eas_idx,uint8_t * pq)1415 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
1416 uint8_t *pq)
1417 {
1418 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1419
1420 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq);
1421 }
1422
1423 static
xive2_router_set_pq(Xive2Router * xrtr,uint8_t eas_blk,uint32_t eas_idx,uint8_t * pq)1424 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
1425 uint8_t *pq)
1426 {
1427 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1428
1429 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq);
1430 }
1431
xive2_router_get_end(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,Xive2End * end)1432 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
1433 Xive2End *end)
1434 {
1435 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1436
1437 return xrc->get_end(xrtr, end_blk, end_idx, end);
1438 }
1439
xive2_router_write_end(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,Xive2End * end,uint8_t word_number)1440 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
1441 Xive2End *end, uint8_t word_number)
1442 {
1443 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1444
1445 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number);
1446 }
1447
xive2_router_get_nvp(Xive2Router * xrtr,uint8_t nvp_blk,uint32_t nvp_idx,Xive2Nvp * nvp)1448 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
1449 Xive2Nvp *nvp)
1450 {
1451 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1452
1453 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp);
1454 }
1455
xive2_router_write_nvp(Xive2Router * xrtr,uint8_t nvp_blk,uint32_t nvp_idx,Xive2Nvp * nvp,uint8_t word_number)1456 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
1457 Xive2Nvp *nvp, uint8_t word_number)
1458 {
1459 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1460
1461 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number);
1462 }
1463
xive2_router_get_nvgc(Xive2Router * xrtr,bool crowd,uint8_t nvgc_blk,uint32_t nvgc_idx,Xive2Nvgc * nvgc)1464 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd,
1465 uint8_t nvgc_blk, uint32_t nvgc_idx,
1466 Xive2Nvgc *nvgc)
1467 {
1468 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1469
1470 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc);
1471 }
1472
xive2_router_write_nvgc(Xive2Router * xrtr,bool crowd,uint8_t nvgc_blk,uint32_t nvgc_idx,Xive2Nvgc * nvgc)1473 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
1474 uint8_t nvgc_blk, uint32_t nvgc_idx,
1475 Xive2Nvgc *nvgc)
1476 {
1477 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
1478
1479 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc);
1480 }
1481
xive2_vp_match_mask(uint32_t cam1,uint32_t cam2,uint32_t vp_mask)1482 static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2,
1483 uint32_t vp_mask)
1484 {
1485 return (cam1 & vp_mask) == (cam2 & vp_mask);
1486 }
1487
xive2_get_vp_block_mask(uint32_t nvt_blk,bool crowd)1488 static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd)
1489 {
1490 uint8_t block_mask = 0b1111;
1491
1492 /* 3 supported crowd sizes: 2, 4, 16 */
1493 if (crowd) {
1494 uint32_t size = xive_get_vpgroup_size(nvt_blk);
1495
1496 if (size != 2 && size != 4 && size != 16) {
1497 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of %d",
1498 size);
1499 return block_mask;
1500 }
1501 block_mask &= ~(size - 1);
1502 }
1503 return block_mask;
1504 }
1505
xive2_get_vp_index_mask(uint32_t nvt_index,bool cam_ignore)1506 static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignore)
1507 {
1508 uint32_t index_mask = 0xFFFFFF; /* 24 bits */
1509
1510 if (cam_ignore) {
1511 uint32_t size = xive_get_vpgroup_size(nvt_index);
1512
1513 if (size < 2) {
1514 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group size of %d",
1515 size);
1516 return index_mask;
1517 }
1518 index_mask &= ~(size - 1);
1519 }
1520 return index_mask;
1521 }
1522
1523 /*
1524 * The thread context register words are in big-endian format.
1525 */
xive2_presenter_tctx_match(XivePresenter * xptr,XiveTCTX * tctx,uint8_t format,uint8_t nvt_blk,uint32_t nvt_idx,bool crowd,bool cam_ignore,uint32_t logic_serv)1526 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
1527 uint8_t format,
1528 uint8_t nvt_blk, uint32_t nvt_idx,
1529 bool crowd, bool cam_ignore,
1530 uint32_t logic_serv)
1531 {
1532 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx);
1533 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
1534 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
1535 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
1536 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
1537
1538 uint32_t index_mask, vp_mask;
1539 uint8_t block_mask;
1540
1541 if (format == 0) {
1542 /*
1543 * i=0: Specific NVT notification
1544 * i=1: VP-group notification (bits ignored at the end of the
1545 * NVT identifier)
1546 */
1547 block_mask = xive2_get_vp_block_mask(nvt_blk, crowd);
1548 index_mask = xive2_get_vp_index_mask(nvt_idx, cam_ignore);
1549 vp_mask = xive2_nvp_cam_line(block_mask, index_mask);
1550
1551 /* For VP-group notifications, threads with LGS=0 are excluded */
1552
1553 /* PHYS ring */
1554 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
1555 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) &&
1556 xive2_vp_match_mask(cam,
1557 xive2_tctx_hw_cam_line(xptr, tctx),
1558 vp_mask)) {
1559 return TM_QW3_HV_PHYS;
1560 }
1561
1562 /* HV POOL ring */
1563 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
1564 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) &&
1565 xive2_vp_match_mask(cam,
1566 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2),
1567 vp_mask)) {
1568 return TM_QW2_HV_POOL;
1569 }
1570
1571 /* OS ring */
1572 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
1573 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) &&
1574 xive2_vp_match_mask(cam,
1575 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2),
1576 vp_mask)) {
1577 return TM_QW1_OS;
1578 }
1579 } else {
1580 /* F=1 : User level Event-Based Branch (EBB) notification */
1581
1582 /* FIXME: what if cam_ignore and LGS = 0 ? */
1583 /* USER ring */
1584 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
1585 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
1586 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) &&
1587 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {
1588 return TM_QW0_USER;
1589 }
1590 }
1591 return -1;
1592 }
1593
xive2_tm_irq_precluded(XiveTCTX * tctx,int ring,uint8_t priority)1594 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority)
1595 {
1596 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
1597
1598 /*
1599 * The xive2_presenter_tctx_match() above tells if there's a match
1600 * but for VP-group notification, we still need to look at the
1601 * priority to know if the thread can take the interrupt now or if
1602 * it is precluded.
1603 */
1604 if (priority < sig_regs[TM_PIPR]) {
1605 return false;
1606 }
1607 return true;
1608 }
1609
xive2_tm_set_lsmfb(XiveTCTX * tctx,int ring,uint8_t priority)1610 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority)
1611 {
1612 uint8_t *regs = &tctx->regs[ring];
1613
1614 /*
1615 * Called by the router during a VP-group notification when the
1616 * thread matches but can't take the interrupt because it's
1617 * already running at a more favored priority. It then stores the
1618 * new interrupt priority in the LSMFB field.
1619 */
1620 regs[TM_LSMFB] = priority;
1621 }
1622
xive2_router_realize(DeviceState * dev,Error ** errp)1623 static void xive2_router_realize(DeviceState *dev, Error **errp)
1624 {
1625 Xive2Router *xrtr = XIVE2_ROUTER(dev);
1626
1627 assert(xrtr->xfb);
1628 }
1629
1630 /*
1631 * Notification using the END ESe/ESn bit (Event State Buffer for
1632 * escalation and notification). Profide further coalescing in the
1633 * Router.
1634 */
xive2_router_end_es_notify(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,Xive2End * end,uint32_t end_esmask)1635 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk,
1636 uint32_t end_idx, Xive2End *end,
1637 uint32_t end_esmask)
1638 {
1639 uint8_t pq = xive_get_field32(end_esmask, end->w1);
1640 bool notify = xive_esb_trigger(&pq);
1641
1642 if (pq != xive_get_field32(end_esmask, end->w1)) {
1643 end->w1 = xive_set_field32(end_esmask, end->w1, pq);
1644 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1);
1645 }
1646
1647 /* ESe/n[Q]=1 : end of notification */
1648 return notify;
1649 }
1650
1651 /*
1652 * An END trigger can come from an event trigger (IPI or HW) or from
1653 * another chip. We don't model the PowerBus but the END trigger
1654 * message has the same parameters than in the function below.
1655 */
xive2_router_end_notify(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,uint32_t end_data,bool redistribute)1656 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
1657 uint32_t end_idx, uint32_t end_data,
1658 bool redistribute)
1659 {
1660 Xive2End end;
1661 uint8_t priority;
1662 uint8_t format;
1663 XiveTCTXMatch match;
1664 bool crowd, cam_ignore;
1665 uint8_t nvx_blk;
1666 uint32_t nvx_idx;
1667
1668 /* END cache lookup */
1669 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) {
1670 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
1671 end_idx);
1672 return;
1673 }
1674
1675 if (!xive2_end_is_valid(&end)) {
1676 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
1677 end_blk, end_idx);
1678 return;
1679 }
1680
1681 if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) {
1682 qemu_log_mask(LOG_GUEST_ERROR,
1683 "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n");
1684 return;
1685 }
1686
1687 if (!redistribute && xive2_end_is_enqueue(&end)) {
1688 trace_xive_end_enqueue(end_blk, end_idx, end_data);
1689 xive2_end_enqueue(&end, end_data);
1690 /* Enqueuing event data modifies the EQ toggle and index */
1691 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1);
1692 }
1693
1694 /*
1695 * When the END is silent, we skip the notification part.
1696 */
1697 if (xive2_end_is_silent_escalation(&end)) {
1698 goto do_escalation;
1699 }
1700
1701 /*
1702 * The W7 format depends on the F bit in W6. It defines the type
1703 * of the notification :
1704 *
1705 * F=0 : single or multiple NVP notification
1706 * F=1 : User level Event-Based Branch (EBB) notification, no
1707 * priority
1708 */
1709 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6);
1710 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7);
1711
1712 /* The END is masked */
1713 if (format == 0 && priority == 0xff) {
1714 return;
1715 }
1716
1717 /*
1718 * Check the END ESn (Event State Buffer for notification) for
1719 * even further coalescing in the Router
1720 */
1721 if (!xive2_end_is_notify(&end)) {
1722 /* ESn[Q]=1 : end of notification */
1723 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
1724 &end, END2_W1_ESn)) {
1725 return;
1726 }
1727 }
1728
1729 /*
1730 * Follows IVPE notification
1731 */
1732 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6);
1733 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6);
1734 crowd = xive2_end_is_crowd(&end);
1735 cam_ignore = xive2_end_is_ignore(&end);
1736
1737 /* TODO: Auto EOI. */
1738 if (xive_presenter_match(xrtr->xfb, format, nvx_blk, nvx_idx,
1739 crowd, cam_ignore, priority,
1740 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7),
1741 &match)) {
1742 XiveTCTX *tctx = match.tctx;
1743 uint8_t ring = match.ring;
1744 uint8_t *sig_regs = xive_tctx_signal_regs(tctx, ring);
1745 uint8_t nsr = sig_regs[TM_NSR];
1746 uint8_t group_level;
1747
1748 if (priority < sig_regs[TM_PIPR] &&
1749 xive_nsr_indicates_group_exception(ring, nsr)) {
1750 xive2_redistribute(xrtr, tctx, xive_nsr_exception_ring(ring, nsr));
1751 }
1752
1753 group_level = xive_get_group_level(crowd, cam_ignore, nvx_blk, nvx_idx);
1754 trace_xive_presenter_notify(nvx_blk, nvx_idx, ring, group_level);
1755 xive_tctx_pipr_present(tctx, ring, priority, group_level);
1756 return;
1757 }
1758
1759 /*
1760 * If no matching NVP is dispatched on a HW thread :
1761 * - specific VP: update the NVP structure if backlog is activated
1762 * - VP-group: update the backlog counter for that priority in the NVG
1763 */
1764 if (xive2_end_is_backlog(&end)) {
1765
1766 if (format == 1) {
1767 qemu_log_mask(LOG_GUEST_ERROR,
1768 "XIVE: END %x/%x invalid config: F1 & backlog\n",
1769 end_blk, end_idx);
1770 return;
1771 }
1772
1773 if (!cam_ignore) {
1774 uint8_t ipb;
1775 Xive2Nvp nvp;
1776
1777 /* NVP cache lookup */
1778 if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) {
1779 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n",
1780 nvx_blk, nvx_idx);
1781 return;
1782 }
1783
1784 if (!xive2_nvp_is_valid(&nvp)) {
1785 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n",
1786 nvx_blk, nvx_idx);
1787 return;
1788 }
1789
1790 /*
1791 * Record the IPB in the associated NVP structure for later
1792 * use. The presenter will resend the interrupt when the vCPU
1793 * is dispatched again on a HW thread.
1794 */
1795 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) |
1796 xive_priority_to_ipb(priority);
1797 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
1798 xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2);
1799 } else {
1800 Xive2Nvgc nvgc;
1801 uint32_t backlog;
1802
1803 /*
1804 * For groups and crowds, the per-priority backlog
1805 * counters are stored in the NVG/NVC structures
1806 */
1807 if (xive2_router_get_nvgc(xrtr, crowd,
1808 nvx_blk, nvx_idx, &nvgc)) {
1809 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n",
1810 crowd ? "NVC" : "NVG", nvx_blk, nvx_idx);
1811 return;
1812 }
1813
1814 if (!xive2_nvgc_is_valid(&nvgc)) {
1815 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid\n",
1816 nvx_blk, nvx_idx);
1817 return;
1818 }
1819
1820 /*
1821 * Increment the backlog counter for that priority.
1822 * We only call broadcast the first time the counter is
1823 * incremented. broadcast will set the LSMFB field of the TIMA of
1824 * relevant threads so that they know an interrupt is pending.
1825 */
1826 backlog = xive2_nvgc_get_backlog(&nvgc, priority) + 1;
1827 xive2_nvgc_set_backlog(&nvgc, priority, backlog);
1828 xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc);
1829
1830 if (backlog == 1) {
1831 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xrtr->xfb);
1832 xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx,
1833 crowd, cam_ignore, priority);
1834
1835 if (!xive2_end_is_precluded_escalation(&end)) {
1836 /*
1837 * The interrupt will be picked up when the
1838 * matching thread lowers its priority level
1839 */
1840 return;
1841 }
1842 }
1843 }
1844 }
1845
1846 do_escalation:
1847 /*
1848 * If activated, escalate notification using the ESe PQ bits and
1849 * the EAS in w4-5
1850 */
1851 if (!xive2_end_is_escalate(&end)) {
1852 return;
1853 }
1854
1855 /*
1856 * Check the END ESe (Event State Buffer for escalation) for even
1857 * further coalescing in the Router
1858 */
1859 if (!xive2_end_is_uncond_escalation(&end)) {
1860 /* ESe[Q]=1 : end of escalation notification */
1861 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
1862 &end, END2_W1_ESe)) {
1863 return;
1864 }
1865 }
1866
1867 if (xive2_end_is_escalate_end(&end)) {
1868 /*
1869 * Perform END Adaptive escalation processing
1870 * The END trigger becomes an Escalation trigger
1871 */
1872 uint8_t esc_blk = xive_get_field32(END2_W4_END_BLOCK, end.w4);
1873 uint32_t esc_idx = xive_get_field32(END2_W4_ESC_END_INDEX, end.w4);
1874 uint32_t esc_data = xive_get_field32(END2_W5_ESC_END_DATA, end.w5);
1875 trace_xive_escalate_end(end_blk, end_idx, esc_blk, esc_idx, esc_data);
1876 xive2_router_end_notify(xrtr, esc_blk, esc_idx, esc_data, false);
1877 } /* end END adaptive escalation */
1878
1879 else {
1880 uint32_t lisn; /* Logical Interrupt Source Number */
1881
1882 /*
1883 * Perform ESB escalation processing
1884 * E[N] == 1 --> N
1885 * Req[Block] <- E[ESB_Block]
1886 * Req[Index] <- E[ESB_Index]
1887 * Req[Offset] <- 0x000
1888 * Execute <ESB Store> Req command
1889 */
1890 lisn = XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4),
1891 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4));
1892
1893 trace_xive_escalate_esb(end_blk, end_idx, lisn);
1894 xive2_notify(xrtr, lisn, true /* pq_checked */);
1895 }
1896
1897 return;
1898 }
1899
xive2_notify(Xive2Router * xrtr,uint32_t lisn,bool pq_checked)1900 void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked)
1901 {
1902 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
1903 uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
1904 Xive2Eas eas;
1905
1906 /* EAS cache lookup */
1907 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) {
1908 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn);
1909 return;
1910 }
1911
1912 if (!pq_checked) {
1913 bool notify;
1914 uint8_t pq;
1915
1916 /* PQ cache lookup */
1917 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) {
1918 /* Set FIR */
1919 g_assert_not_reached();
1920 }
1921
1922 notify = xive_esb_trigger(&pq);
1923
1924 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) {
1925 /* Set FIR */
1926 g_assert_not_reached();
1927 }
1928
1929 if (!notify) {
1930 return;
1931 }
1932 }
1933
1934 if (!xive2_eas_is_valid(&eas)) {
1935 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn);
1936 return;
1937 }
1938
1939 if (xive2_eas_is_masked(&eas)) {
1940 /* Notification completed */
1941 return;
1942 }
1943
1944 /* TODO: add support for EAS resume */
1945 if (xive2_eas_is_resume(&eas)) {
1946 qemu_log_mask(LOG_UNIMP,
1947 "XIVE: EAS resume processing unimplemented - LISN %x\n",
1948 lisn);
1949 return;
1950 }
1951
1952 /*
1953 * The event trigger becomes an END trigger
1954 */
1955 xive2_router_end_notify(xrtr,
1956 xive_get_field64(EAS2_END_BLOCK, eas.w),
1957 xive_get_field64(EAS2_END_INDEX, eas.w),
1958 xive_get_field64(EAS2_END_DATA, eas.w),
1959 false);
1960 return;
1961 }
1962
xive2_router_notify(XiveNotifier * xn,uint32_t lisn,bool pq_checked)1963 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
1964 {
1965 Xive2Router *xrtr = XIVE2_ROUTER(xn);
1966
1967 xive2_notify(xrtr, lisn, pq_checked);
1968 return;
1969 }
1970
1971 static const Property xive2_router_properties[] = {
1972 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb,
1973 TYPE_XIVE_FABRIC, XiveFabric *),
1974 };
1975
xive2_router_class_init(ObjectClass * klass,const void * data)1976 static void xive2_router_class_init(ObjectClass *klass, const void *data)
1977 {
1978 DeviceClass *dc = DEVICE_CLASS(klass);
1979 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
1980
1981 dc->desc = "XIVE2 Router Engine";
1982 device_class_set_props(dc, xive2_router_properties);
1983 /* Parent is SysBusDeviceClass. No need to call its realize hook */
1984 dc->realize = xive2_router_realize;
1985 xnc->notify = xive2_router_notify;
1986 }
1987
1988 static const TypeInfo xive2_router_info = {
1989 .name = TYPE_XIVE2_ROUTER,
1990 .parent = TYPE_SYS_BUS_DEVICE,
1991 .abstract = true,
1992 .instance_size = sizeof(Xive2Router),
1993 .class_size = sizeof(Xive2RouterClass),
1994 .class_init = xive2_router_class_init,
1995 .interfaces = (const InterfaceInfo[]) {
1996 { TYPE_XIVE_NOTIFIER },
1997 { TYPE_XIVE_PRESENTER },
1998 { }
1999 }
2000 };
2001
addr_is_even(hwaddr addr,uint32_t shift)2002 static inline bool addr_is_even(hwaddr addr, uint32_t shift)
2003 {
2004 return !((addr >> shift) & 1);
2005 }
2006
xive2_end_source_read(void * opaque,hwaddr addr,unsigned size)2007 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size)
2008 {
2009 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
2010 uint32_t offset = addr & 0xFFF;
2011 uint8_t end_blk;
2012 uint32_t end_idx;
2013 Xive2End end;
2014 uint32_t end_esmask;
2015 uint8_t pq;
2016 uint64_t ret;
2017
2018 /*
2019 * The block id should be deduced from the load address on the END
2020 * ESB MMIO but our model only supports a single block per XIVE chip.
2021 */
2022 end_blk = xive2_router_get_block_id(xsrc->xrtr);
2023 end_idx = addr >> (xsrc->esb_shift + 1);
2024
2025 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
2026 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
2027 end_idx);
2028 return -1;
2029 }
2030
2031 if (!xive2_end_is_valid(&end)) {
2032 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
2033 end_blk, end_idx);
2034 return -1;
2035 }
2036
2037 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
2038 END2_W1_ESe;
2039 pq = xive_get_field32(end_esmask, end.w1);
2040
2041 switch (offset) {
2042 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
2043 ret = xive_esb_eoi(&pq);
2044
2045 /* Forward the source event notification for routing ?? */
2046 break;
2047
2048 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
2049 ret = pq;
2050 break;
2051
2052 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
2053 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
2054 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
2055 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
2056 ret = xive_esb_set(&pq, (offset >> 8) & 0x3);
2057 break;
2058 default:
2059 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n",
2060 offset);
2061 return -1;
2062 }
2063
2064 if (pq != xive_get_field32(end_esmask, end.w1)) {
2065 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
2066 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
2067 }
2068
2069 return ret;
2070 }
2071
xive2_end_source_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)2072 static void xive2_end_source_write(void *opaque, hwaddr addr,
2073 uint64_t value, unsigned size)
2074 {
2075 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
2076 uint32_t offset = addr & 0xFFF;
2077 uint8_t end_blk;
2078 uint32_t end_idx;
2079 Xive2End end;
2080 uint32_t end_esmask;
2081 uint8_t pq;
2082 bool notify = false;
2083
2084 /*
2085 * The block id should be deduced from the load address on the END
2086 * ESB MMIO but our model only supports a single block per XIVE chip.
2087 */
2088 end_blk = xive2_router_get_block_id(xsrc->xrtr);
2089 end_idx = addr >> (xsrc->esb_shift + 1);
2090
2091 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
2092 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
2093 end_idx);
2094 return;
2095 }
2096
2097 if (!xive2_end_is_valid(&end)) {
2098 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
2099 end_blk, end_idx);
2100 return;
2101 }
2102
2103 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
2104 END2_W1_ESe;
2105 pq = xive_get_field32(end_esmask, end.w1);
2106
2107 switch (offset) {
2108 case 0 ... 0x3FF:
2109 notify = xive_esb_trigger(&pq);
2110 break;
2111
2112 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF:
2113 /* TODO: can we check StoreEOI availability from the router ? */
2114 notify = xive_esb_eoi(&pq);
2115 break;
2116
2117 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
2118 if (end_esmask == END2_W1_ESe) {
2119 qemu_log_mask(LOG_GUEST_ERROR,
2120 "XIVE: END %x/%x can not EQ inject on ESe\n",
2121 end_blk, end_idx);
2122 return;
2123 }
2124 notify = true;
2125 break;
2126
2127 default:
2128 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n",
2129 offset);
2130 return;
2131 }
2132
2133 if (pq != xive_get_field32(end_esmask, end.w1)) {
2134 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
2135 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
2136 }
2137
2138 /* TODO: Forward the source event notification for routing */
2139 if (notify) {
2140 ;
2141 }
2142 }
2143
2144 static const MemoryRegionOps xive2_end_source_ops = {
2145 .read = xive2_end_source_read,
2146 .write = xive2_end_source_write,
2147 .endianness = DEVICE_BIG_ENDIAN,
2148 .valid = {
2149 .min_access_size = 1,
2150 .max_access_size = 8,
2151 },
2152 .impl = {
2153 .min_access_size = 1,
2154 .max_access_size = 8,
2155 },
2156 };
2157
xive2_end_source_realize(DeviceState * dev,Error ** errp)2158 static void xive2_end_source_realize(DeviceState *dev, Error **errp)
2159 {
2160 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev);
2161
2162 assert(xsrc->xrtr);
2163
2164 if (!xsrc->nr_ends) {
2165 error_setg(errp, "Number of interrupt needs to be greater than 0");
2166 return;
2167 }
2168
2169 if (xsrc->esb_shift != XIVE_ESB_4K &&
2170 xsrc->esb_shift != XIVE_ESB_64K) {
2171 error_setg(errp, "Invalid ESB shift setting");
2172 return;
2173 }
2174
2175 /*
2176 * Each END is assigned an even/odd pair of MMIO pages, the even page
2177 * manages the ESn field while the odd page manages the ESe field.
2178 */
2179 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc),
2180 &xive2_end_source_ops, xsrc, "xive.end",
2181 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends);
2182 }
2183
2184 static const Property xive2_end_source_properties[] = {
2185 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0),
2186 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K),
2187 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER,
2188 Xive2Router *),
2189 };
2190
xive2_end_source_class_init(ObjectClass * klass,const void * data)2191 static void xive2_end_source_class_init(ObjectClass *klass, const void *data)
2192 {
2193 DeviceClass *dc = DEVICE_CLASS(klass);
2194
2195 dc->desc = "XIVE END Source";
2196 device_class_set_props(dc, xive2_end_source_properties);
2197 dc->realize = xive2_end_source_realize;
2198 dc->user_creatable = false;
2199 }
2200
2201 static const TypeInfo xive2_end_source_info = {
2202 .name = TYPE_XIVE2_END_SOURCE,
2203 .parent = TYPE_DEVICE,
2204 .instance_size = sizeof(Xive2EndSource),
2205 .class_init = xive2_end_source_class_init,
2206 };
2207
xive2_register_types(void)2208 static void xive2_register_types(void)
2209 {
2210 type_register_static(&xive2_router_info);
2211 type_register_static(&xive2_end_source_info);
2212 }
2213
2214 type_init(xive2_register_types)
2215