1 /*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation..
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/ppc/xive.h"
19 #include "hw/ppc/xive2.h"
20 #include "hw/ppc/xive2_regs.h"
21
xive2_router_get_config(Xive2Router * xrtr)22 uint32_t xive2_router_get_config(Xive2Router *xrtr)
23 {
24 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
25
26 return xrc->get_config(xrtr);
27 }
28
xive2_router_get_block_id(Xive2Router * xrtr)29 static int xive2_router_get_block_id(Xive2Router *xrtr)
30 {
31 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
32
33 return xrc->get_block_id(xrtr);
34 }
35
xive2_nvp_reporting_addr(Xive2Nvp * nvp)36 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp)
37 {
38 uint64_t cache_addr;
39
40 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 |
41 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7);
42 cache_addr <<= 8; /* aligned on a cache line pair */
43 return cache_addr;
44 }
45
xive2_nvgc_get_backlog(Xive2Nvgc * nvgc,uint8_t priority)46 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority)
47 {
48 uint32_t val = 0;
49 uint8_t *ptr, i;
50
51 if (priority > 7) {
52 return 0;
53 }
54
55 /*
56 * The per-priority backlog counters are 24-bit and the structure
57 * is stored in big endian
58 */
59 ptr = (uint8_t *)&nvgc->w2 + priority * 3;
60 for (i = 0; i < 3; i++, ptr++) {
61 val = (val << 8) + *ptr;
62 }
63 return val;
64 }
65
xive2_eas_pic_print_info(Xive2Eas * eas,uint32_t lisn,GString * buf)66 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
67 {
68 if (!xive2_eas_is_valid(eas)) {
69 return;
70 }
71
72 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n",
73 lisn, xive2_eas_is_masked(eas) ? "M" : " ",
74 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
75 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
76 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
77 }
78
xive2_end_queue_pic_print_info(Xive2End * end,uint32_t width,GString * buf)79 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf)
80 {
81 uint64_t qaddr_base = xive2_end_qaddr(end);
82 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
83 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
84 uint32_t qentries = 1 << (qsize + 10);
85 int i;
86
87 /*
88 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
89 */
90 g_string_append_printf(buf, " [ ");
91 qindex = (qindex - (width - 1)) & (qentries - 1);
92 for (i = 0; i < width; i++) {
93 uint64_t qaddr = qaddr_base + (qindex << 2);
94 uint32_t qdata = -1;
95
96 if (dma_memory_read(&address_space_memory, qaddr, &qdata,
97 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) {
98 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%"
99 HWADDR_PRIx "\n", qaddr);
100 return;
101 }
102 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "",
103 be32_to_cpu(qdata));
104 qindex = (qindex + 1) & (qentries - 1);
105 }
106 g_string_append_printf(buf, "]");
107 }
108
xive2_end_pic_print_info(Xive2End * end,uint32_t end_idx,GString * buf)109 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf)
110 {
111 uint64_t qaddr_base = xive2_end_qaddr(end);
112 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
113 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
114 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
115 uint32_t qentries = 1 << (qsize + 10);
116
117 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6);
118 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6);
119 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7);
120 uint8_t pq;
121
122 if (!xive2_end_is_valid(end)) {
123 return;
124 }
125
126 pq = xive_get_field32(END2_W1_ESn, end->w1);
127
128 g_string_append_printf(buf,
129 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c "
130 "prio:%d nvp:%02x/%04x",
131 end_idx,
132 pq & XIVE_ESB_VAL_P ? 'P' : '-',
133 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
134 xive2_end_is_valid(end) ? 'v' : '-',
135 xive2_end_is_enqueue(end) ? 'q' : '-',
136 xive2_end_is_notify(end) ? 'n' : '-',
137 xive2_end_is_backlog(end) ? 'b' : '-',
138 xive2_end_is_precluded_escalation(end) ? 'p' : '-',
139 xive2_end_is_escalate(end) ? 'e' : '-',
140 xive2_end_is_escalate_end(end) ? 'N' : '-',
141 xive2_end_is_uncond_escalation(end) ? 'u' : '-',
142 xive2_end_is_silent_escalation(end) ? 's' : '-',
143 xive2_end_is_firmware1(end) ? 'f' : '-',
144 xive2_end_is_firmware2(end) ? 'F' : '-',
145 xive2_end_is_ignore(end) ? 'i' : '-',
146 xive2_end_is_crowd(end) ? 'c' : '-',
147 priority, nvp_blk, nvp_idx);
148
149 if (qaddr_base) {
150 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d",
151 qaddr_base, qindex, qentries, qgen);
152 xive2_end_queue_pic_print_info(end, 6, buf);
153 }
154 g_string_append_c(buf, '\n');
155 }
156
xive2_end_eas_pic_print_info(Xive2End * end,uint32_t end_idx,GString * buf)157 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
158 GString *buf)
159 {
160 Xive2Eas *eas = (Xive2Eas *) &end->w4;
161 uint8_t pq;
162
163 if (!xive2_end_is_escalate(end)) {
164 return;
165 }
166
167 pq = xive_get_field32(END2_W1_ESe, end->w1);
168
169 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
170 end_idx,
171 pq & XIVE_ESB_VAL_P ? 'P' : '-',
172 pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
173 xive2_eas_is_valid(eas) ? 'v' : ' ',
174 xive2_eas_is_masked(eas) ? 'M' : ' ',
175 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
176 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
177 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
178 }
179
xive2_nvp_pic_print_info(Xive2Nvp * nvp,uint32_t nvp_idx,GString * buf)180 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf)
181 {
182 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
183 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
184 uint64_t cache_line = xive2_nvp_reporting_addr(nvp);
185
186 if (!xive2_nvp_is_valid(nvp)) {
187 return;
188 }
189
190 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x",
191 nvp_idx, eq_blk, eq_idx,
192 xive_get_field32(NVP2_W2_IPB, nvp->w2),
193 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0));
194 if (cache_line) {
195 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line);
196 }
197
198 /*
199 * When the NVP is HW controlled, more fields are updated
200 */
201 if (xive2_nvp_is_hw(nvp)) {
202 g_string_append_printf(buf, " CPPR:%02x",
203 xive_get_field32(NVP2_W2_CPPR, nvp->w2));
204 if (xive2_nvp_is_co(nvp)) {
205 g_string_append_printf(buf, " CO:%04x",
206 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));
207 }
208 }
209 g_string_append_c(buf, '\n');
210 }
211
xive2_nvgc_pic_print_info(Xive2Nvgc * nvgc,uint32_t nvgc_idx,GString * buf)212 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf)
213 {
214 uint8_t i;
215
216 if (!xive2_nvgc_is_valid(nvgc)) {
217 return;
218 }
219
220 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx,
221 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0));
222 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) {
223 g_string_append_printf(buf, "[%d]=0x%x ",
224 i, xive2_nvgc_get_backlog(nvgc, i));
225 }
226 g_string_append_printf(buf, "\n");
227 }
228
xive2_end_enqueue(Xive2End * end,uint32_t data)229 static void xive2_end_enqueue(Xive2End *end, uint32_t data)
230 {
231 uint64_t qaddr_base = xive2_end_qaddr(end);
232 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
233 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
234 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
235
236 uint64_t qaddr = qaddr_base + (qindex << 2);
237 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));
238 uint32_t qentries = 1 << (qsize + 10);
239
240 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata),
241 MEMTXATTRS_UNSPECIFIED)) {
242 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%"
243 HWADDR_PRIx "\n", qaddr);
244 return;
245 }
246
247 qindex = (qindex + 1) & (qentries - 1);
248 if (qindex == 0) {
249 qgen ^= 1;
250 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen);
251
252 /* TODO(PowerNV): reset GF bit on a cache watch operation */
253 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen);
254 }
255 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
256 }
257
258 /*
259 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
260 *
261 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit
262 *
263 * - if a context is enabled with the H bit set, the VP context
264 * information is retrieved from the NVP structure (“check out”)
265 * and stored back on a context pull (“check in”), the SW receives
266 * the same context pull information as on P9
267 *
268 * - the H bit cannot be changed while the V bit is set, i.e. a
269 * context cannot be set up in the TIMA and then be “pushed” into
270 * the NVP by changing the H bit while the context is enabled
271 */
272
xive2_tctx_save_ctx(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t nvp_blk,uint32_t nvp_idx,uint8_t ring)273 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
274 uint8_t nvp_blk, uint32_t nvp_idx,
275 uint8_t ring)
276 {
277 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
278 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
279 Xive2Nvp nvp;
280 uint8_t *regs = &tctx->regs[ring];
281
282 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
283 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
284 nvp_blk, nvp_idx);
285 return;
286 }
287
288 if (!xive2_nvp_is_valid(&nvp)) {
289 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
290 nvp_blk, nvp_idx);
291 return;
292 }
293
294 if (!xive2_nvp_is_hw(&nvp)) {
295 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
296 nvp_blk, nvp_idx);
297 return;
298 }
299
300 if (!xive2_nvp_is_co(&nvp)) {
301 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n",
302 nvp_blk, nvp_idx);
303 return;
304 }
305
306 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) &&
307 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) {
308 qemu_log_mask(LOG_GUEST_ERROR,
309 "XIVE: NVP %x/%x invalid checkout Thread %x\n",
310 nvp_blk, nvp_idx, pir);
311 return;
312 }
313
314 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
315 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);
316 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
317 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
318
319 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
320 /* NVP2_W1_CO_THRID_VALID only set once */
321 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF);
322 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);
323 }
324
xive2_cam_decode(uint32_t cam,uint8_t * nvp_blk,uint32_t * nvp_idx,bool * valid,bool * hw)325 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk,
326 uint32_t *nvp_idx, bool *valid, bool *hw)
327 {
328 *nvp_blk = xive2_nvp_blk(cam);
329 *nvp_idx = xive2_nvp_idx(cam);
330 *valid = !!(cam & TM2_W2_VALID);
331 *hw = !!(cam & TM2_W2_HW);
332 }
333
334 /*
335 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id
336 * width and block id width is configurable at the IC level.
337 *
338 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit)
339 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit)
340 */
xive2_tctx_hw_cam_line(XivePresenter * xptr,XiveTCTX * tctx)341 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
342 {
343 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
344 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
345 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
346 uint8_t blk = xive2_router_get_block_id(xrtr);
347 uint8_t tid_shift =
348 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7;
349 uint8_t tid_mask = (1 << tid_shift) - 1;
350
351 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));
352 }
353
xive2_tm_pull_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,unsigned size,uint8_t ring)354 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx,
355 hwaddr offset, unsigned size, uint8_t ring)
356 {
357 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
358 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]);
359 uint32_t cam = be32_to_cpu(target_ringw2);
360 uint8_t nvp_blk;
361 uint32_t nvp_idx;
362 uint8_t cur_ring;
363 bool valid;
364 bool do_save;
365
366 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save);
367
368 if (!valid) {
369 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
370 nvp_blk, nvp_idx);
371 }
372
373 /* Invalidate CAM line of requested ring and all lower rings */
374 for (cur_ring = TM_QW0_USER; cur_ring <= ring;
375 cur_ring += XIVE_TM_RING_SIZE) {
376 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]);
377 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0);
378 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4);
379 }
380
381 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {
382 xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring);
383 }
384
385 /*
386 * Lower external interrupt line of requested ring and below except for
387 * USER, which doesn't exist.
388 */
389 for (cur_ring = TM_QW1_OS; cur_ring <= ring;
390 cur_ring += XIVE_TM_RING_SIZE) {
391 xive_tctx_reset_signal(tctx, cur_ring);
392 }
393 return target_ringw2;
394 }
395
xive2_tm_pull_os_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,unsigned size)396 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
397 hwaddr offset, unsigned size)
398 {
399 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS);
400 }
401
402 #define REPORT_LINE_GEN1_SIZE 16
403
xive2_tm_report_line_gen1(XiveTCTX * tctx,uint8_t * data,uint8_t size)404 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data,
405 uint8_t size)
406 {
407 uint8_t *regs = tctx->regs;
408
409 g_assert(size == REPORT_LINE_GEN1_SIZE);
410 memset(data, 0, size);
411 /*
412 * See xive architecture for description of what is saved. It is
413 * hand-picked information to fit in 16 bytes.
414 */
415 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR];
416 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR];
417 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB];
418 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB];
419 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT];
420 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS];
421 data[0x6] = 0xFF;
422 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80;
423 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1;
424 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2;
425 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3);
426 data[0x8] = regs[TM_QW1_OS + TM_NSR];
427 data[0x9] = regs[TM_QW1_OS + TM_CPPR];
428 data[0xA] = regs[TM_QW1_OS + TM_IPB];
429 data[0xB] = regs[TM_QW1_OS + TM_LGS];
430 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) {
431 /*
432 * Logical server extension, except VU bit replaced by EB bit
433 * from NSR
434 */
435 data[0xC] = regs[TM_QW0_USER + TM_WORD2];
436 data[0xC] &= ~0x80;
437 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80;
438 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1];
439 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2];
440 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3];
441 }
442 }
443
xive2_tm_pull_ctx_ol(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size,uint8_t ring)444 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
445 hwaddr offset, uint64_t value,
446 unsigned size, uint8_t ring)
447 {
448 Xive2Router *xrtr = XIVE2_ROUTER(xptr);
449 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved;
450 uint8_t nvp_blk;
451 Xive2Nvp nvp;
452 uint64_t phys_addr;
453 MemTxResult result;
454
455 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx);
456 nvp_blk = xive2_nvp_blk(hw_cam);
457 nvp_idx = xive2_nvp_idx(hw_cam);
458
459 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
460 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
461 nvp_blk, nvp_idx);
462 return;
463 }
464
465 if (!xive2_nvp_is_valid(&nvp)) {
466 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
467 nvp_blk, nvp_idx);
468 return;
469 }
470
471 xive2_cfg = xive2_router_get_config(xrtr);
472
473 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */
474 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) {
475 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE];
476
477 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE);
478 result = dma_memory_write(&address_space_memory, phys_addr,
479 pull_ctxt, REPORT_LINE_GEN1_SIZE,
480 MEMTXATTRS_UNSPECIFIED);
481 assert(result == MEMTX_OK);
482 } else {
483 result = dma_memory_write(&address_space_memory, phys_addr,
484 &tctx->regs, sizeof(tctx->regs),
485 MEMTXATTRS_UNSPECIFIED);
486 assert(result == MEMTX_OK);
487 reserved = 0xFFFFFFFF;
488 result = dma_memory_write(&address_space_memory, phys_addr + 12,
489 &reserved, sizeof(reserved),
490 MEMTXATTRS_UNSPECIFIED);
491 assert(result == MEMTX_OK);
492 }
493
494 /* the rest is similar to pull context to registers */
495 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring);
496 }
497
xive2_tm_pull_os_ctx_ol(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)498 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
499 hwaddr offset, uint64_t value, unsigned size)
500 {
501 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS);
502 }
503
504
xive2_tm_pull_phys_ctx_ol(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)505 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
506 hwaddr offset, uint64_t value, unsigned size)
507 {
508 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS);
509 }
510
xive2_tctx_restore_os_ctx(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t nvp_blk,uint32_t nvp_idx,Xive2Nvp * nvp)511 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
512 uint8_t nvp_blk, uint32_t nvp_idx,
513 Xive2Nvp *nvp)
514 {
515 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
516 uint32_t pir = env->spr_cb[SPR_PIR].default_value;
517 uint8_t cppr;
518
519 if (!xive2_nvp_is_hw(nvp)) {
520 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
521 nvp_blk, nvp_idx);
522 return 0;
523 }
524
525 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2);
526 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0);
527 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
528
529 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr;
530 /* we don't model LSMFB */
531
532 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
533 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);
534 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir);
535
536 /*
537 * Checkout privilege: 0:OS, 1:Pool, 2:Hard
538 *
539 * TODO: we only support OS push/pull
540 */
541 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0);
542
543 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1);
544
545 /* return restored CPPR to generate a CPU exception if needed */
546 return cppr;
547 }
548
xive2_tctx_need_resend(Xive2Router * xrtr,XiveTCTX * tctx,uint8_t nvp_blk,uint32_t nvp_idx,bool do_restore)549 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
550 uint8_t nvp_blk, uint32_t nvp_idx,
551 bool do_restore)
552 {
553 Xive2Nvp nvp;
554 uint8_t ipb;
555
556 /*
557 * Grab the associated thread interrupt context registers in the
558 * associated NVP
559 */
560 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
561 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
562 nvp_blk, nvp_idx);
563 return;
564 }
565
566 if (!xive2_nvp_is_valid(&nvp)) {
567 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
568 nvp_blk, nvp_idx);
569 return;
570 }
571
572 /* Automatically restore thread context registers */
573 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE &&
574 do_restore) {
575 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp);
576 }
577
578 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
579 if (ipb) {
580 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
581 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
582 }
583 /*
584 * Always call xive_tctx_ipb_update(). Even if there were no
585 * escalation triggered, there could be a pending interrupt which
586 * was saved when the context was pulled and that we need to take
587 * into account by recalculating the PIPR (which is not
588 * saved/restored).
589 * It will also raise the External interrupt signal if needed.
590 */
591 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
592 }
593
594 /*
595 * Updating the OS CAM line can trigger a resend of interrupt
596 */
xive2_tm_push_os_ctx(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)597 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
598 hwaddr offset, uint64_t value, unsigned size)
599 {
600 uint32_t cam;
601 uint32_t qw1w2;
602 uint64_t qw1dw1;
603 uint8_t nvp_blk;
604 uint32_t nvp_idx;
605 bool vo;
606 bool do_restore;
607
608 /* First update the thead context */
609 switch (size) {
610 case 4:
611 cam = value;
612 qw1w2 = cpu_to_be32(cam);
613 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
614 break;
615 case 8:
616 cam = value >> 32;
617 qw1dw1 = cpu_to_be64(value);
618 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8);
619 break;
620 default:
621 g_assert_not_reached();
622 }
623
624 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
625
626 /* Check the interrupt pending bits */
627 if (vo) {
628 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx,
629 do_restore);
630 }
631 }
632
xive2_tctx_set_target(XiveTCTX * tctx,uint8_t ring,uint8_t target)633 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target)
634 {
635 uint8_t *regs = &tctx->regs[ring];
636
637 regs[TM_T] = target;
638 }
639
xive2_tm_set_hv_target(XivePresenter * xptr,XiveTCTX * tctx,hwaddr offset,uint64_t value,unsigned size)640 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
641 hwaddr offset, uint64_t value, unsigned size)
642 {
643 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff);
644 }
645
646 /*
647 * XIVE Router (aka. Virtualization Controller or IVRE)
648 */
649
xive2_router_get_eas(Xive2Router * xrtr,uint8_t eas_blk,uint32_t eas_idx,Xive2Eas * eas)650 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
651 Xive2Eas *eas)
652 {
653 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
654
655 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
656 }
657
658 static
xive2_router_get_pq(Xive2Router * xrtr,uint8_t eas_blk,uint32_t eas_idx,uint8_t * pq)659 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
660 uint8_t *pq)
661 {
662 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
663
664 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq);
665 }
666
667 static
xive2_router_set_pq(Xive2Router * xrtr,uint8_t eas_blk,uint32_t eas_idx,uint8_t * pq)668 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
669 uint8_t *pq)
670 {
671 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
672
673 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq);
674 }
675
xive2_router_get_end(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,Xive2End * end)676 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
677 Xive2End *end)
678 {
679 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
680
681 return xrc->get_end(xrtr, end_blk, end_idx, end);
682 }
683
xive2_router_write_end(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,Xive2End * end,uint8_t word_number)684 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
685 Xive2End *end, uint8_t word_number)
686 {
687 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
688
689 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number);
690 }
691
xive2_router_get_nvp(Xive2Router * xrtr,uint8_t nvp_blk,uint32_t nvp_idx,Xive2Nvp * nvp)692 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
693 Xive2Nvp *nvp)
694 {
695 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
696
697 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp);
698 }
699
xive2_router_write_nvp(Xive2Router * xrtr,uint8_t nvp_blk,uint32_t nvp_idx,Xive2Nvp * nvp,uint8_t word_number)700 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
701 Xive2Nvp *nvp, uint8_t word_number)
702 {
703 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
704
705 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number);
706 }
707
xive2_router_get_nvgc(Xive2Router * xrtr,bool crowd,uint8_t nvgc_blk,uint32_t nvgc_idx,Xive2Nvgc * nvgc)708 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd,
709 uint8_t nvgc_blk, uint32_t nvgc_idx,
710 Xive2Nvgc *nvgc)
711 {
712 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
713
714 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc);
715 }
716
xive2_router_write_nvgc(Xive2Router * xrtr,bool crowd,uint8_t nvgc_blk,uint32_t nvgc_idx,Xive2Nvgc * nvgc)717 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd,
718 uint8_t nvgc_blk, uint32_t nvgc_idx,
719 Xive2Nvgc *nvgc)
720 {
721 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
722
723 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc);
724 }
725
726 /*
727 * The thread context register words are in big-endian format.
728 */
xive2_presenter_tctx_match(XivePresenter * xptr,XiveTCTX * tctx,uint8_t format,uint8_t nvt_blk,uint32_t nvt_idx,bool cam_ignore,uint32_t logic_serv)729 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
730 uint8_t format,
731 uint8_t nvt_blk, uint32_t nvt_idx,
732 bool cam_ignore, uint32_t logic_serv)
733 {
734 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx);
735 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
736 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
737 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
738 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
739
740 /*
741 * TODO (PowerNV): ignore mode. The low order bits of the NVT
742 * identifier are ignored in the "CAM" match.
743 */
744
745 if (format == 0) {
746 if (cam_ignore == true) {
747 /*
748 * F=0 & i=1: Logical server notification (bits ignored at
749 * the end of the NVT identifier)
750 */
751 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
752 nvt_blk, nvt_idx);
753 return -1;
754 }
755
756 /* F=0 & i=0: Specific NVT notification */
757
758 /* PHYS ring */
759 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
760 cam == xive2_tctx_hw_cam_line(xptr, tctx)) {
761 return TM_QW3_HV_PHYS;
762 }
763
764 /* HV POOL ring */
765 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
766 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {
767 return TM_QW2_HV_POOL;
768 }
769
770 /* OS ring */
771 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
772 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {
773 return TM_QW1_OS;
774 }
775 } else {
776 /* F=1 : User level Event-Based Branch (EBB) notification */
777
778 /* USER ring */
779 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
780 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
781 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) &&
782 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {
783 return TM_QW0_USER;
784 }
785 }
786 return -1;
787 }
788
xive2_router_realize(DeviceState * dev,Error ** errp)789 static void xive2_router_realize(DeviceState *dev, Error **errp)
790 {
791 Xive2Router *xrtr = XIVE2_ROUTER(dev);
792
793 assert(xrtr->xfb);
794 }
795
796 /*
797 * Notification using the END ESe/ESn bit (Event State Buffer for
798 * escalation and notification). Profide further coalescing in the
799 * Router.
800 */
xive2_router_end_es_notify(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,Xive2End * end,uint32_t end_esmask)801 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk,
802 uint32_t end_idx, Xive2End *end,
803 uint32_t end_esmask)
804 {
805 uint8_t pq = xive_get_field32(end_esmask, end->w1);
806 bool notify = xive_esb_trigger(&pq);
807
808 if (pq != xive_get_field32(end_esmask, end->w1)) {
809 end->w1 = xive_set_field32(end_esmask, end->w1, pq);
810 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1);
811 }
812
813 /* ESe/n[Q]=1 : end of notification */
814 return notify;
815 }
816
817 /*
818 * An END trigger can come from an event trigger (IPI or HW) or from
819 * another chip. We don't model the PowerBus but the END trigger
820 * message has the same parameters than in the function below.
821 */
xive2_router_end_notify(Xive2Router * xrtr,uint8_t end_blk,uint32_t end_idx,uint32_t end_data)822 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
823 uint32_t end_idx, uint32_t end_data)
824 {
825 Xive2End end;
826 uint8_t priority;
827 uint8_t format;
828 bool found;
829 Xive2Nvp nvp;
830 uint8_t nvp_blk;
831 uint32_t nvp_idx;
832
833 /* END cache lookup */
834 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) {
835 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
836 end_idx);
837 return;
838 }
839
840 if (!xive2_end_is_valid(&end)) {
841 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
842 end_blk, end_idx);
843 return;
844 }
845
846 if (xive2_end_is_enqueue(&end)) {
847 xive2_end_enqueue(&end, end_data);
848 /* Enqueuing event data modifies the EQ toggle and index */
849 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1);
850 }
851
852 /*
853 * When the END is silent, we skip the notification part.
854 */
855 if (xive2_end_is_silent_escalation(&end)) {
856 goto do_escalation;
857 }
858
859 /*
860 * The W7 format depends on the F bit in W6. It defines the type
861 * of the notification :
862 *
863 * F=0 : single or multiple NVP notification
864 * F=1 : User level Event-Based Branch (EBB) notification, no
865 * priority
866 */
867 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6);
868 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7);
869
870 /* The END is masked */
871 if (format == 0 && priority == 0xff) {
872 return;
873 }
874
875 /*
876 * Check the END ESn (Event State Buffer for notification) for
877 * even further coalescing in the Router
878 */
879 if (!xive2_end_is_notify(&end)) {
880 /* ESn[Q]=1 : end of notification */
881 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
882 &end, END2_W1_ESn)) {
883 return;
884 }
885 }
886
887 /*
888 * Follows IVPE notification
889 */
890 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6);
891 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6);
892
893 /* NVP cache lookup */
894 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
895 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n",
896 nvp_blk, nvp_idx);
897 return;
898 }
899
900 if (!xive2_nvp_is_valid(&nvp)) {
901 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n",
902 nvp_blk, nvp_idx);
903 return;
904 }
905
906 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
907 xive2_end_is_ignore(&end),
908 priority,
909 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7));
910
911 /* TODO: Auto EOI. */
912
913 if (found) {
914 return;
915 }
916
917 /*
918 * If no matching NVP is dispatched on a HW thread :
919 * - specific VP: update the NVP structure if backlog is activated
920 * - logical server : forward request to IVPE (not supported)
921 */
922 if (xive2_end_is_backlog(&end)) {
923 uint8_t ipb;
924
925 if (format == 1) {
926 qemu_log_mask(LOG_GUEST_ERROR,
927 "XIVE: END %x/%x invalid config: F1 & backlog\n",
928 end_blk, end_idx);
929 return;
930 }
931
932 /*
933 * Record the IPB in the associated NVP structure for later
934 * use. The presenter will resend the interrupt when the vCPU
935 * is dispatched again on a HW thread.
936 */
937 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) |
938 xive_priority_to_ipb(priority);
939 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
940 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
941
942 /*
943 * On HW, follows a "Broadcast Backlog" to IVPEs
944 */
945 }
946
947 do_escalation:
948 /*
949 * If activated, escalate notification using the ESe PQ bits and
950 * the EAS in w4-5
951 */
952 if (!xive2_end_is_escalate(&end)) {
953 return;
954 }
955
956 /*
957 * Check the END ESe (Event State Buffer for escalation) for even
958 * further coalescing in the Router
959 */
960 if (!xive2_end_is_uncond_escalation(&end)) {
961 /* ESe[Q]=1 : end of escalation notification */
962 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
963 &end, END2_W1_ESe)) {
964 return;
965 }
966 }
967
968 /*
969 * The END trigger becomes an Escalation trigger
970 */
971 xive2_router_end_notify(xrtr,
972 xive_get_field32(END2_W4_END_BLOCK, end.w4),
973 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),
974 xive_get_field32(END2_W5_ESC_END_DATA, end.w5));
975 }
976
xive2_router_notify(XiveNotifier * xn,uint32_t lisn,bool pq_checked)977 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
978 {
979 Xive2Router *xrtr = XIVE2_ROUTER(xn);
980 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
981 uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
982 Xive2Eas eas;
983
984 /* EAS cache lookup */
985 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) {
986 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn);
987 return;
988 }
989
990 if (!pq_checked) {
991 bool notify;
992 uint8_t pq;
993
994 /* PQ cache lookup */
995 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) {
996 /* Set FIR */
997 g_assert_not_reached();
998 }
999
1000 notify = xive_esb_trigger(&pq);
1001
1002 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) {
1003 /* Set FIR */
1004 g_assert_not_reached();
1005 }
1006
1007 if (!notify) {
1008 return;
1009 }
1010 }
1011
1012 if (!xive2_eas_is_valid(&eas)) {
1013 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn);
1014 return;
1015 }
1016
1017 if (xive2_eas_is_masked(&eas)) {
1018 /* Notification completed */
1019 return;
1020 }
1021
1022 /*
1023 * The event trigger becomes an END trigger
1024 */
1025 xive2_router_end_notify(xrtr,
1026 xive_get_field64(EAS2_END_BLOCK, eas.w),
1027 xive_get_field64(EAS2_END_INDEX, eas.w),
1028 xive_get_field64(EAS2_END_DATA, eas.w));
1029 }
1030
1031 static Property xive2_router_properties[] = {
1032 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb,
1033 TYPE_XIVE_FABRIC, XiveFabric *),
1034 DEFINE_PROP_END_OF_LIST(),
1035 };
1036
xive2_router_class_init(ObjectClass * klass,void * data)1037 static void xive2_router_class_init(ObjectClass *klass, void *data)
1038 {
1039 DeviceClass *dc = DEVICE_CLASS(klass);
1040 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
1041
1042 dc->desc = "XIVE2 Router Engine";
1043 device_class_set_props(dc, xive2_router_properties);
1044 /* Parent is SysBusDeviceClass. No need to call its realize hook */
1045 dc->realize = xive2_router_realize;
1046 xnc->notify = xive2_router_notify;
1047 }
1048
1049 static const TypeInfo xive2_router_info = {
1050 .name = TYPE_XIVE2_ROUTER,
1051 .parent = TYPE_SYS_BUS_DEVICE,
1052 .abstract = true,
1053 .instance_size = sizeof(Xive2Router),
1054 .class_size = sizeof(Xive2RouterClass),
1055 .class_init = xive2_router_class_init,
1056 .interfaces = (InterfaceInfo[]) {
1057 { TYPE_XIVE_NOTIFIER },
1058 { TYPE_XIVE_PRESENTER },
1059 { }
1060 }
1061 };
1062
addr_is_even(hwaddr addr,uint32_t shift)1063 static inline bool addr_is_even(hwaddr addr, uint32_t shift)
1064 {
1065 return !((addr >> shift) & 1);
1066 }
1067
xive2_end_source_read(void * opaque,hwaddr addr,unsigned size)1068 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size)
1069 {
1070 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
1071 uint32_t offset = addr & 0xFFF;
1072 uint8_t end_blk;
1073 uint32_t end_idx;
1074 Xive2End end;
1075 uint32_t end_esmask;
1076 uint8_t pq;
1077 uint64_t ret;
1078
1079 /*
1080 * The block id should be deduced from the load address on the END
1081 * ESB MMIO but our model only supports a single block per XIVE chip.
1082 */
1083 end_blk = xive2_router_get_block_id(xsrc->xrtr);
1084 end_idx = addr >> (xsrc->esb_shift + 1);
1085
1086 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
1087 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
1088 end_idx);
1089 return -1;
1090 }
1091
1092 if (!xive2_end_is_valid(&end)) {
1093 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
1094 end_blk, end_idx);
1095 return -1;
1096 }
1097
1098 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
1099 END2_W1_ESe;
1100 pq = xive_get_field32(end_esmask, end.w1);
1101
1102 switch (offset) {
1103 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
1104 ret = xive_esb_eoi(&pq);
1105
1106 /* Forward the source event notification for routing ?? */
1107 break;
1108
1109 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
1110 ret = pq;
1111 break;
1112
1113 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
1114 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
1115 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
1116 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
1117 ret = xive_esb_set(&pq, (offset >> 8) & 0x3);
1118 break;
1119 default:
1120 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n",
1121 offset);
1122 return -1;
1123 }
1124
1125 if (pq != xive_get_field32(end_esmask, end.w1)) {
1126 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
1127 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
1128 }
1129
1130 return ret;
1131 }
1132
xive2_end_source_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)1133 static void xive2_end_source_write(void *opaque, hwaddr addr,
1134 uint64_t value, unsigned size)
1135 {
1136 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
1137 uint32_t offset = addr & 0xFFF;
1138 uint8_t end_blk;
1139 uint32_t end_idx;
1140 Xive2End end;
1141 uint32_t end_esmask;
1142 uint8_t pq;
1143 bool notify = false;
1144
1145 /*
1146 * The block id should be deduced from the load address on the END
1147 * ESB MMIO but our model only supports a single block per XIVE chip.
1148 */
1149 end_blk = xive2_router_get_block_id(xsrc->xrtr);
1150 end_idx = addr >> (xsrc->esb_shift + 1);
1151
1152 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
1153 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
1154 end_idx);
1155 return;
1156 }
1157
1158 if (!xive2_end_is_valid(&end)) {
1159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
1160 end_blk, end_idx);
1161 return;
1162 }
1163
1164 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
1165 END2_W1_ESe;
1166 pq = xive_get_field32(end_esmask, end.w1);
1167
1168 switch (offset) {
1169 case 0 ... 0x3FF:
1170 notify = xive_esb_trigger(&pq);
1171 break;
1172
1173 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF:
1174 /* TODO: can we check StoreEOI availability from the router ? */
1175 notify = xive_esb_eoi(&pq);
1176 break;
1177
1178 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
1179 if (end_esmask == END2_W1_ESe) {
1180 qemu_log_mask(LOG_GUEST_ERROR,
1181 "XIVE: END %x/%x can not EQ inject on ESe\n",
1182 end_blk, end_idx);
1183 return;
1184 }
1185 notify = true;
1186 break;
1187
1188 default:
1189 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n",
1190 offset);
1191 return;
1192 }
1193
1194 if (pq != xive_get_field32(end_esmask, end.w1)) {
1195 end.w1 = xive_set_field32(end_esmask, end.w1, pq);
1196 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
1197 }
1198
1199 /* TODO: Forward the source event notification for routing */
1200 if (notify) {
1201 ;
1202 }
1203 }
1204
1205 static const MemoryRegionOps xive2_end_source_ops = {
1206 .read = xive2_end_source_read,
1207 .write = xive2_end_source_write,
1208 .endianness = DEVICE_BIG_ENDIAN,
1209 .valid = {
1210 .min_access_size = 1,
1211 .max_access_size = 8,
1212 },
1213 .impl = {
1214 .min_access_size = 1,
1215 .max_access_size = 8,
1216 },
1217 };
1218
xive2_end_source_realize(DeviceState * dev,Error ** errp)1219 static void xive2_end_source_realize(DeviceState *dev, Error **errp)
1220 {
1221 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev);
1222
1223 assert(xsrc->xrtr);
1224
1225 if (!xsrc->nr_ends) {
1226 error_setg(errp, "Number of interrupt needs to be greater than 0");
1227 return;
1228 }
1229
1230 if (xsrc->esb_shift != XIVE_ESB_4K &&
1231 xsrc->esb_shift != XIVE_ESB_64K) {
1232 error_setg(errp, "Invalid ESB shift setting");
1233 return;
1234 }
1235
1236 /*
1237 * Each END is assigned an even/odd pair of MMIO pages, the even page
1238 * manages the ESn field while the odd page manages the ESe field.
1239 */
1240 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc),
1241 &xive2_end_source_ops, xsrc, "xive.end",
1242 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends);
1243 }
1244
1245 static Property xive2_end_source_properties[] = {
1246 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0),
1247 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K),
1248 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER,
1249 Xive2Router *),
1250 DEFINE_PROP_END_OF_LIST(),
1251 };
1252
xive2_end_source_class_init(ObjectClass * klass,void * data)1253 static void xive2_end_source_class_init(ObjectClass *klass, void *data)
1254 {
1255 DeviceClass *dc = DEVICE_CLASS(klass);
1256
1257 dc->desc = "XIVE END Source";
1258 device_class_set_props(dc, xive2_end_source_properties);
1259 dc->realize = xive2_end_source_realize;
1260 dc->user_creatable = false;
1261 }
1262
1263 static const TypeInfo xive2_end_source_info = {
1264 .name = TYPE_XIVE2_END_SOURCE,
1265 .parent = TYPE_DEVICE,
1266 .instance_size = sizeof(Xive2EndSource),
1267 .class_init = xive2_end_source_class_init,
1268 };
1269
xive2_register_types(void)1270 static void xive2_register_types(void)
1271 {
1272 type_register_static(&xive2_router_info);
1273 type_register_static(&xive2_end_source_info);
1274 }
1275
1276 type_init(xive2_register_types)
1277