1 /*
2 * QEMU model of Xilinx uartlite.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/log.h"
27 #include "hw/char/xilinx_uartlite.h"
28 #include "hw/irq.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
31 #include "hw/sysbus.h"
32 #include "qemu/module.h"
33 #include "chardev/char-fe.h"
34 #include "qom/object.h"
35
36 #define DUART(x)
37
38 #define R_RX 0
39 #define R_TX 1
40 #define R_STATUS 2
41 #define R_CTRL 3
42 #define R_MAX 4
43
44 #define STATUS_RXVALID 0x01
45 #define STATUS_RXFULL 0x02
46 #define STATUS_TXEMPTY 0x04
47 #define STATUS_TXFULL 0x08
48 #define STATUS_IE 0x10
49 #define STATUS_OVERRUN 0x20
50 #define STATUS_FRAME 0x40
51 #define STATUS_PARITY 0x80
52
53 #define CONTROL_RST_TX 0x01
54 #define CONTROL_RST_RX 0x02
55 #define CONTROL_IE 0x10
56
57 struct XilinxUARTLite {
58 SysBusDevice parent_obj;
59
60 MemoryRegion mmio;
61 CharBackend chr;
62 qemu_irq irq;
63
64 uint8_t rx_fifo[8];
65 unsigned int rx_fifo_pos;
66 unsigned int rx_fifo_len;
67
68 uint32_t regs[R_MAX];
69 };
70
uart_update_irq(XilinxUARTLite * s)71 static void uart_update_irq(XilinxUARTLite *s)
72 {
73 unsigned int irq;
74
75 if (s->rx_fifo_len)
76 s->regs[R_STATUS] |= STATUS_IE;
77
78 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
79 qemu_set_irq(s->irq, irq);
80 }
81
uart_update_status(XilinxUARTLite * s)82 static void uart_update_status(XilinxUARTLite *s)
83 {
84 uint32_t r;
85
86 r = s->regs[R_STATUS];
87 r &= ~7;
88 r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
89 r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
90 r |= (!!s->rx_fifo_len);
91 s->regs[R_STATUS] = r;
92 }
93
xilinx_uartlite_reset(DeviceState * dev)94 static void xilinx_uartlite_reset(DeviceState *dev)
95 {
96 uart_update_status(XILINX_UARTLITE(dev));
97 }
98
99 static uint64_t
uart_read(void * opaque,hwaddr addr,unsigned int size)100 uart_read(void *opaque, hwaddr addr, unsigned int size)
101 {
102 XilinxUARTLite *s = opaque;
103 uint32_t r = 0;
104 addr >>= 2;
105 switch (addr)
106 {
107 case R_RX:
108 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
109 if (s->rx_fifo_len)
110 s->rx_fifo_len--;
111 uart_update_status(s);
112 uart_update_irq(s);
113 qemu_chr_fe_accept_input(&s->chr);
114 break;
115
116 default:
117 if (addr < ARRAY_SIZE(s->regs))
118 r = s->regs[addr];
119 DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
120 break;
121 }
122 return r;
123 }
124
125 static void
uart_write(void * opaque,hwaddr addr,uint64_t val64,unsigned int size)126 uart_write(void *opaque, hwaddr addr,
127 uint64_t val64, unsigned int size)
128 {
129 XilinxUARTLite *s = opaque;
130 uint32_t value = val64;
131 unsigned char ch = value;
132
133 addr >>= 2;
134 switch (addr)
135 {
136 case R_STATUS:
137 qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
138 __func__);
139 break;
140
141 case R_CTRL:
142 if (value & CONTROL_RST_RX) {
143 s->rx_fifo_pos = 0;
144 s->rx_fifo_len = 0;
145 }
146 s->regs[addr] = value;
147 break;
148
149 case R_TX:
150 /* XXX this blocks entire thread. Rewrite to use
151 * qemu_chr_fe_write and background I/O callbacks */
152 qemu_chr_fe_write_all(&s->chr, &ch, 1);
153 s->regs[addr] = value;
154
155 /* hax. */
156 s->regs[R_STATUS] |= STATUS_IE;
157 break;
158
159 default:
160 DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
161 if (addr < ARRAY_SIZE(s->regs))
162 s->regs[addr] = value;
163 break;
164 }
165 uart_update_status(s);
166 uart_update_irq(s);
167 }
168
169 static const MemoryRegionOps uart_ops = {
170 .read = uart_read,
171 .write = uart_write,
172 .endianness = DEVICE_NATIVE_ENDIAN,
173 .valid = {
174 .min_access_size = 1,
175 .max_access_size = 4
176 }
177 };
178
179 static Property xilinx_uartlite_properties[] = {
180 DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
181 DEFINE_PROP_END_OF_LIST(),
182 };
183
uart_rx(void * opaque,const uint8_t * buf,int size)184 static void uart_rx(void *opaque, const uint8_t *buf, int size)
185 {
186 XilinxUARTLite *s = opaque;
187
188 /* Got a byte. */
189 if (s->rx_fifo_len >= 8) {
190 printf("WARNING: UART dropped char.\n");
191 return;
192 }
193 s->rx_fifo[s->rx_fifo_pos] = *buf;
194 s->rx_fifo_pos++;
195 s->rx_fifo_pos &= 0x7;
196 s->rx_fifo_len++;
197
198 uart_update_status(s);
199 uart_update_irq(s);
200 }
201
uart_can_rx(void * opaque)202 static int uart_can_rx(void *opaque)
203 {
204 XilinxUARTLite *s = opaque;
205
206 return s->rx_fifo_len < sizeof(s->rx_fifo);
207 }
208
uart_event(void * opaque,QEMUChrEvent event)209 static void uart_event(void *opaque, QEMUChrEvent event)
210 {
211
212 }
213
xilinx_uartlite_realize(DeviceState * dev,Error ** errp)214 static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
215 {
216 XilinxUARTLite *s = XILINX_UARTLITE(dev);
217
218 qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
219 uart_event, NULL, s, NULL, true);
220 }
221
xilinx_uartlite_init(Object * obj)222 static void xilinx_uartlite_init(Object *obj)
223 {
224 XilinxUARTLite *s = XILINX_UARTLITE(obj);
225
226 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
227
228 memory_region_init_io(&s->mmio, obj, &uart_ops, s,
229 "xlnx.xps-uartlite", R_MAX * 4);
230 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
231 }
232
xilinx_uartlite_class_init(ObjectClass * klass,void * data)233 static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
234 {
235 DeviceClass *dc = DEVICE_CLASS(klass);
236
237 device_class_set_legacy_reset(dc, xilinx_uartlite_reset);
238 dc->realize = xilinx_uartlite_realize;
239 device_class_set_props(dc, xilinx_uartlite_properties);
240 }
241
242 static const TypeInfo xilinx_uartlite_info = {
243 .name = TYPE_XILINX_UARTLITE,
244 .parent = TYPE_SYS_BUS_DEVICE,
245 .instance_size = sizeof(XilinxUARTLite),
246 .instance_init = xilinx_uartlite_init,
247 .class_init = xilinx_uartlite_class_init,
248 };
249
xilinx_uart_register_types(void)250 static void xilinx_uart_register_types(void)
251 {
252 type_register_static(&xilinx_uartlite_info);
253 }
254
255 type_init(xilinx_uart_register_types)
256