xref: /openbmc/linux/drivers/mtd/spi-nor/xilinx.c (revision d534fd97)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2005, Intec Automation Inc.
4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
5  */
6 
7 #include <linux/mtd/spi-nor.h>
8 
9 #include "core.h"
10 
11 #define XILINX_OP_SE		0x50	/* Sector erase */
12 #define XILINX_OP_PP		0x82	/* Page program */
13 #define XILINX_OP_RDSR		0xd7	/* Read status register */
14 
15 #define XSR_PAGESIZE		BIT(0)	/* Page size in Po2 or Linear */
16 #define XSR_RDY			BIT(7)	/* Ready */
17 
18 #define XILINX_RDSR_OP(buf)						\
19 	SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0),			\
20 		   SPI_MEM_OP_NO_ADDR,					\
21 		   SPI_MEM_OP_NO_DUMMY,					\
22 		   SPI_MEM_OP_DATA_IN(1, buf, 0))
23 
24 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size)			\
25 		.id = {							\
26 			((_jedec_id) >> 16) & 0xff,			\
27 			((_jedec_id) >> 8) & 0xff,			\
28 			(_jedec_id) & 0xff				\
29 			},						\
30 		.id_len = 3,						\
31 		.sector_size = (8 * (_page_size)),			\
32 		.n_sectors = (_n_sectors),				\
33 		.page_size = (_page_size),				\
34 		.n_banks = 1,						\
35 		.addr_nbytes = 3,					\
36 		.flags = SPI_NOR_NO_FR
37 
38 /* Xilinx S3AN share MFR with Atmel SPI NOR */
39 static const struct flash_info xilinx_nor_parts[] = {
40 	/* Xilinx S3AN Internal Flash */
41 	{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
42 	{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
43 	{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
44 	{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
45 	{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
46 };
47 
48 /*
49  * This code converts an address to the Default Address Mode, that has non
50  * power of two page sizes. We must support this mode because it is the default
51  * mode supported by Xilinx tools, it can access the whole flash area and
52  * changing over to the Power-of-two mode is irreversible and corrupts the
53  * original data.
54  * Addr can safely be unsigned int, the biggest S3AN device is smaller than
55  * 4 MiB.
56  */
s3an_nor_convert_addr(struct spi_nor * nor,u32 addr)57 static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
58 {
59 	u32 page_size = nor->params->page_size;
60 	u32 offset, page;
61 
62 	offset = addr % page_size;
63 	page = addr / page_size;
64 	page <<= (page_size > 512) ? 10 : 9;
65 
66 	return page | offset;
67 }
68 
69 /**
70  * xilinx_nor_read_sr() - Read the Status Register on S3AN flashes.
71  * @nor:	pointer to 'struct spi_nor'.
72  * @sr:		pointer to a DMA-able buffer where the value of the
73  *              Status Register will be written.
74  *
75  * Return: 0 on success, -errno otherwise.
76  */
xilinx_nor_read_sr(struct spi_nor * nor,u8 * sr)77 static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
78 {
79 	int ret;
80 
81 	if (nor->spimem) {
82 		struct spi_mem_op op = XILINX_RDSR_OP(sr);
83 
84 		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
85 
86 		ret = spi_mem_exec_op(nor->spimem, &op);
87 	} else {
88 		ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr,
89 						      1);
90 	}
91 
92 	if (ret)
93 		dev_dbg(nor->dev, "error %d reading SR\n", ret);
94 
95 	return ret;
96 }
97 
98 /**
99  * xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see
100  * if the flash is ready for new commands.
101  * @nor:	pointer to 'struct spi_nor'.
102  *
103  * Return: 1 if ready, 0 if not ready, -errno on errors.
104  */
xilinx_nor_sr_ready(struct spi_nor * nor)105 static int xilinx_nor_sr_ready(struct spi_nor *nor)
106 {
107 	int ret;
108 
109 	ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
110 	if (ret)
111 		return ret;
112 
113 	return !!(nor->bouncebuf[0] & XSR_RDY);
114 }
115 
xilinx_nor_setup(struct spi_nor * nor,const struct spi_nor_hwcaps * hwcaps)116 static int xilinx_nor_setup(struct spi_nor *nor,
117 			    const struct spi_nor_hwcaps *hwcaps)
118 {
119 	u32 page_size;
120 	int ret;
121 
122 	ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
123 	if (ret)
124 		return ret;
125 
126 	nor->erase_opcode = XILINX_OP_SE;
127 	nor->program_opcode = XILINX_OP_PP;
128 	nor->read_opcode = SPINOR_OP_READ;
129 	nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
130 
131 	/*
132 	 * This flashes have a page size of 264 or 528 bytes (known as
133 	 * Default addressing mode). It can be changed to a more standard
134 	 * Power of two mode where the page size is 256/512. This comes
135 	 * with a price: there is 3% less of space, the data is corrupted
136 	 * and the page size cannot be changed back to default addressing
137 	 * mode.
138 	 *
139 	 * The current addressing mode can be read from the XRDSR register
140 	 * and should not be changed, because is a destructive operation.
141 	 */
142 	if (nor->bouncebuf[0] & XSR_PAGESIZE) {
143 		/* Flash in Power of 2 mode */
144 		page_size = (nor->params->page_size == 264) ? 256 : 512;
145 		nor->params->page_size = page_size;
146 		nor->mtd.writebufsize = page_size;
147 		nor->params->size = 8 * page_size * nor->info->n_sectors;
148 		nor->mtd.erasesize = 8 * page_size;
149 	} else {
150 		/* Flash in Default addressing mode */
151 		nor->params->convert_addr = s3an_nor_convert_addr;
152 		nor->mtd.erasesize = nor->info->sector_size;
153 	}
154 
155 	return 0;
156 }
157 
xilinx_nor_late_init(struct spi_nor * nor)158 static int xilinx_nor_late_init(struct spi_nor *nor)
159 {
160 	nor->params->setup = xilinx_nor_setup;
161 	nor->params->ready = xilinx_nor_sr_ready;
162 
163 	return 0;
164 }
165 
166 static const struct spi_nor_fixups xilinx_nor_fixups = {
167 	.late_init = xilinx_nor_late_init,
168 };
169 
170 const struct spi_nor_manufacturer spi_nor_xilinx = {
171 	.name = "xilinx",
172 	.parts = xilinx_nor_parts,
173 	.nparts = ARRAY_SIZE(xilinx_nor_parts),
174 	.fixups = &xilinx_nor_fixups,
175 };
176