xref: /openbmc/linux/drivers/usb/host/xhci-hub.c (revision d7cdfc31)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * xHCI host controller driver
4  *
5  * Copyright (C) 2008 Intel Corp.
6  *
7  * Author: Sarah Sharp
8  * Some code borrowed from the Linux EHCI driver.
9  */
10 
11 
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14 #include <linux/bitfield.h>
15 
16 #include "xhci.h"
17 #include "xhci-trace.h"
18 
19 #define	PORT_WAKE_BITS	(PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
20 #define	PORT_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
21 			 PORT_RC | PORT_PLC | PORT_PE)
22 
23 /* Default sublink speed attribute of each lane */
24 static u32 ssp_cap_default_ssa[] = {
25 	0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 	0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 	0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 	0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 	0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 	0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 	0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 	0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
33 };
34 
xhci_create_usb3x_bos_desc(struct xhci_hcd * xhci,char * buf,u16 wLength)35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf,
36 				      u16 wLength)
37 {
38 	struct usb_bos_descriptor	*bos;
39 	struct usb_ss_cap_descriptor	*ss_cap;
40 	struct usb_ssp_cap_descriptor	*ssp_cap;
41 	struct xhci_port_cap		*port_cap = NULL;
42 	u16				bcdUSB;
43 	u32				reg;
44 	u32				min_rate = 0;
45 	u8				min_ssid;
46 	u8				ssac;
47 	u8				ssic;
48 	int				offset;
49 	int				i;
50 
51 	/* BOS descriptor */
52 	bos = (struct usb_bos_descriptor *)buf;
53 	bos->bLength = USB_DT_BOS_SIZE;
54 	bos->bDescriptorType = USB_DT_BOS;
55 	bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
56 					USB_DT_USB_SS_CAP_SIZE);
57 	bos->bNumDeviceCaps = 1;
58 
59 	/* Create the descriptor for port with the highest revision */
60 	for (i = 0; i < xhci->num_port_caps; i++) {
61 		u8 major = xhci->port_caps[i].maj_rev;
62 		u8 minor = xhci->port_caps[i].min_rev;
63 		u16 rev = (major << 8) | minor;
64 
65 		if (i == 0 || bcdUSB < rev) {
66 			bcdUSB = rev;
67 			port_cap = &xhci->port_caps[i];
68 		}
69 	}
70 
71 	if (bcdUSB >= 0x0310) {
72 		if (port_cap->psi_count) {
73 			u8 num_sym_ssa = 0;
74 
75 			for (i = 0; i < port_cap->psi_count; i++) {
76 				if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM)
77 					num_sym_ssa++;
78 			}
79 
80 			ssac = port_cap->psi_count + num_sym_ssa - 1;
81 			ssic = port_cap->psi_uid_count - 1;
82 		} else {
83 			if (bcdUSB >= 0x0320)
84 				ssac = 7;
85 			else
86 				ssac = 3;
87 
88 			ssic = (ssac + 1) / 2 - 1;
89 		}
90 
91 		bos->bNumDeviceCaps++;
92 		bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
93 						USB_DT_USB_SS_CAP_SIZE +
94 						USB_DT_USB_SSP_CAP_SIZE(ssac));
95 	}
96 
97 	if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
98 		return wLength;
99 
100 	/* SuperSpeed USB Device Capability */
101 	ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE];
102 	ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
103 	ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
104 	ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
105 	ss_cap->bmAttributes = 0; /* set later */
106 	ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION);
107 	ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
108 	ss_cap->bU1devExitLat = 0; /* set later */
109 	ss_cap->bU2DevExitLat = 0; /* set later */
110 
111 	reg = readl(&xhci->cap_regs->hcc_params);
112 	if (HCC_LTC(reg))
113 		ss_cap->bmAttributes |= USB_LTM_SUPPORT;
114 
115 	if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
116 		reg = readl(&xhci->cap_regs->hcs_params3);
117 		ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg);
118 		ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg));
119 	}
120 
121 	if (wLength < le16_to_cpu(bos->wTotalLength))
122 		return wLength;
123 
124 	if (bcdUSB < 0x0310)
125 		return le16_to_cpu(bos->wTotalLength);
126 
127 	ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE +
128 		USB_DT_USB_SS_CAP_SIZE];
129 	ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
130 	ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
131 	ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
132 	ssp_cap->bReserved = 0;
133 	ssp_cap->wReserved = 0;
134 	ssp_cap->bmAttributes =
135 		cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
136 			    FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
137 
138 	if (!port_cap->psi_count) {
139 		for (i = 0; i < ssac + 1; i++)
140 			ssp_cap->bmSublinkSpeedAttr[i] =
141 				cpu_to_le32(ssp_cap_default_ssa[i]);
142 
143 		min_ssid = 4;
144 		goto out;
145 	}
146 
147 	offset = 0;
148 	for (i = 0; i < port_cap->psi_count; i++) {
149 		u32 psi;
150 		u32 attr;
151 		u8 ssid;
152 		u8 lp;
153 		u8 lse;
154 		u8 psie;
155 		u16 lane_mantissa;
156 		u16 psim;
157 		u16 plt;
158 
159 		psi = port_cap->psi[i];
160 		ssid = XHCI_EXT_PORT_PSIV(psi);
161 		lp = XHCI_EXT_PORT_LP(psi);
162 		psie = XHCI_EXT_PORT_PSIE(psi);
163 		psim = XHCI_EXT_PORT_PSIM(psi);
164 		plt = psi & PLT_MASK;
165 
166 		lse = psie;
167 		lane_mantissa = psim;
168 
169 		/* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
170 		for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++)
171 			psim /= 1000;
172 
173 		if (!min_rate || psim < min_rate) {
174 			min_ssid = ssid;
175 			min_rate = psim;
176 		}
177 
178 		/* Some host controllers don't set the link protocol for SSP */
179 		if (psim >= 10)
180 			lp = USB_SSP_SUBLINK_SPEED_LP_SSP;
181 
182 		/*
183 		 * PSIM and PSIE represent the total speed of PSI. The BOS
184 		 * descriptor SSP sublink speed attribute lane mantissa
185 		 * describes the lane speed. E.g. PSIM and PSIE for gen2x2
186 		 * is 20Gbps, but the BOS descriptor lane speed mantissa is
187 		 * 10Gbps. Check and modify the mantissa value to match the
188 		 * lane speed.
189 		 */
190 		if (bcdUSB == 0x0320 && plt == PLT_SYM) {
191 			/*
192 			 * The PSI dword for gen1x2 and gen2x1 share the same
193 			 * values. But the lane speed for gen1x2 is 5Gbps while
194 			 * gen2x1 is 10Gbps. If the previous PSI dword SSID is
195 			 * 5 and the PSIE and PSIM match with SSID 6, let's
196 			 * assume that the controller follows the default speed
197 			 * id with SSID 6 for gen1x2.
198 			 */
199 			if (ssid == 6 && psie == 3 && psim == 10 && i) {
200 				u32 prev = port_cap->psi[i - 1];
201 
202 				if ((prev & PLT_MASK) == PLT_SYM &&
203 				    XHCI_EXT_PORT_PSIV(prev) == 5 &&
204 				    XHCI_EXT_PORT_PSIE(prev) == 3 &&
205 				    XHCI_EXT_PORT_PSIM(prev) == 10) {
206 					lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
207 					lane_mantissa = 5;
208 				}
209 			}
210 
211 			if (psie == 3 && psim > 10) {
212 				lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
213 				lane_mantissa = 10;
214 			}
215 		}
216 
217 		attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
218 			FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) |
219 			FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) |
220 			FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa));
221 
222 		switch (plt) {
223 		case PLT_SYM:
224 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
225 					   USB_SSP_SUBLINK_SPEED_ST_SYM_RX);
226 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
227 
228 			attr &= ~USB_SSP_SUBLINK_SPEED_ST;
229 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
230 					   USB_SSP_SUBLINK_SPEED_ST_SYM_TX);
231 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
232 			break;
233 		case PLT_ASYM_RX:
234 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
235 					   USB_SSP_SUBLINK_SPEED_ST_ASYM_RX);
236 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
237 			break;
238 		case PLT_ASYM_TX:
239 			attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
240 					   USB_SSP_SUBLINK_SPEED_ST_ASYM_TX);
241 			ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
242 			break;
243 		}
244 	}
245 out:
246 	ssp_cap->wFunctionalitySupport =
247 		cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID,
248 				       min_ssid) |
249 			    FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
250 			    FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
251 
252 	return le16_to_cpu(bos->wTotalLength);
253 }
254 
xhci_common_hub_descriptor(struct xhci_hcd * xhci,struct usb_hub_descriptor * desc,int ports)255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
256 		struct usb_hub_descriptor *desc, int ports)
257 {
258 	u16 temp;
259 
260 	desc->bHubContrCurrent = 0;
261 
262 	desc->bNbrPorts = ports;
263 	temp = 0;
264 	/* Bits 1:0 - support per-port power switching, or power always on */
265 	if (HCC_PPC(xhci->hcc_params))
266 		temp |= HUB_CHAR_INDV_PORT_LPSM;
267 	else
268 		temp |= HUB_CHAR_NO_LPSM;
269 	/* Bit  2 - root hubs are not part of a compound device */
270 	/* Bits 4:3 - individual port over current protection */
271 	temp |= HUB_CHAR_INDV_PORT_OCPM;
272 	/* Bits 6:5 - no TTs in root ports */
273 	/* Bit  7 - no port indicators */
274 	desc->wHubCharacteristics = cpu_to_le16(temp);
275 }
276 
277 /* Fill in the USB 2.0 roothub descriptor */
xhci_usb2_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
279 		struct usb_hub_descriptor *desc)
280 {
281 	int ports;
282 	u16 temp;
283 	__u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
284 	u32 portsc;
285 	unsigned int i;
286 	struct xhci_hub *rhub;
287 
288 	rhub = &xhci->usb2_rhub;
289 	ports = rhub->num_ports;
290 	xhci_common_hub_descriptor(xhci, desc, ports);
291 	desc->bDescriptorType = USB_DT_HUB;
292 	temp = 1 + (ports / 8);
293 	desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
294 	desc->bPwrOn2PwrGood = 10;	/* xhci section 5.4.8 says 20ms */
295 
296 	/* The Device Removable bits are reported on a byte granularity.
297 	 * If the port doesn't exist within that byte, the bit is set to 0.
298 	 */
299 	memset(port_removable, 0, sizeof(port_removable));
300 	for (i = 0; i < ports; i++) {
301 		portsc = readl(rhub->ports[i]->addr);
302 		/* If a device is removable, PORTSC reports a 0, same as in the
303 		 * hub descriptor DeviceRemovable bits.
304 		 */
305 		if (portsc & PORT_DEV_REMOVE)
306 			/* This math is hairy because bit 0 of DeviceRemovable
307 			 * is reserved, and bit 1 is for port 1, etc.
308 			 */
309 			port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
310 	}
311 
312 	/* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
313 	 * ports on it.  The USB 2.0 specification says that there are two
314 	 * variable length fields at the end of the hub descriptor:
315 	 * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
316 	 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
317 	 * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
318 	 * 0xFF, so we initialize the both arrays (DeviceRemovable and
319 	 * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
320 	 * set of ports that actually exist.
321 	 */
322 	memset(desc->u.hs.DeviceRemovable, 0xff,
323 			sizeof(desc->u.hs.DeviceRemovable));
324 	memset(desc->u.hs.PortPwrCtrlMask, 0xff,
325 			sizeof(desc->u.hs.PortPwrCtrlMask));
326 
327 	for (i = 0; i < (ports + 1 + 7) / 8; i++)
328 		memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
329 				sizeof(__u8));
330 }
331 
332 /* Fill in the USB 3.0 roothub descriptor */
xhci_usb3_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
334 		struct usb_hub_descriptor *desc)
335 {
336 	int ports;
337 	u16 port_removable;
338 	u32 portsc;
339 	unsigned int i;
340 	struct xhci_hub *rhub;
341 
342 	rhub = &xhci->usb3_rhub;
343 	ports = rhub->num_ports;
344 	xhci_common_hub_descriptor(xhci, desc, ports);
345 	desc->bDescriptorType = USB_DT_SS_HUB;
346 	desc->bDescLength = USB_DT_SS_HUB_SIZE;
347 	desc->bPwrOn2PwrGood = 50;	/* usb 3.1 may fail if less than 100ms */
348 
349 	/* header decode latency should be zero for roothubs,
350 	 * see section 4.23.5.2.
351 	 */
352 	desc->u.ss.bHubHdrDecLat = 0;
353 	desc->u.ss.wHubDelay = 0;
354 
355 	port_removable = 0;
356 	/* bit 0 is reserved, bit 1 is for port 1, etc. */
357 	for (i = 0; i < ports; i++) {
358 		portsc = readl(rhub->ports[i]->addr);
359 		if (portsc & PORT_DEV_REMOVE)
360 			port_removable |= 1 << (i + 1);
361 	}
362 
363 	desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
364 }
365 
xhci_hub_descriptor(struct usb_hcd * hcd,struct xhci_hcd * xhci,struct usb_hub_descriptor * desc)366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
367 		struct usb_hub_descriptor *desc)
368 {
369 
370 	if (hcd->speed >= HCD_USB3)
371 		xhci_usb3_hub_descriptor(hcd, xhci, desc);
372 	else
373 		xhci_usb2_hub_descriptor(hcd, xhci, desc);
374 
375 }
376 
xhci_port_speed(unsigned int port_status)377 static unsigned int xhci_port_speed(unsigned int port_status)
378 {
379 	if (DEV_LOWSPEED(port_status))
380 		return USB_PORT_STAT_LOW_SPEED;
381 	if (DEV_HIGHSPEED(port_status))
382 		return USB_PORT_STAT_HIGH_SPEED;
383 	/*
384 	 * FIXME: Yes, we should check for full speed, but the core uses that as
385 	 * a default in portspeed() in usb/core/hub.c (which is the only place
386 	 * USB_PORT_STAT_*_SPEED is used).
387 	 */
388 	return 0;
389 }
390 
391 /*
392  * These bits are Read Only (RO) and should be saved and written to the
393  * registers: 0, 3, 10:13, 30
394  * connect status, over-current status, port speed, and device removable.
395  * connect status and port speed are also sticky - meaning they're in
396  * the AUX well and they aren't changed by a hot, warm, or cold reset.
397  */
398 #define	XHCI_PORT_RO	((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
399 /*
400  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
401  * bits 5:8, 9, 14:15, 25:27
402  * link state, port power, port indicator state, "wake on" enable state
403  */
404 #define XHCI_PORT_RWS	((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
405 /*
406  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
407  * bit 4 (port reset)
408  */
409 #define	XHCI_PORT_RW1S	((1<<4))
410 /*
411  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
412  * bits 1, 17, 18, 19, 20, 21, 22, 23
413  * port enable/disable, and
414  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
415  * over-current, reset, link state, and L1 change
416  */
417 #define XHCI_PORT_RW1CS	((1<<1) | (0x7f<<17))
418 /*
419  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
420  * latched in
421  */
422 #define	XHCI_PORT_RW	((1<<16))
423 /*
424  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
425  * bits 2, 24, 28:31
426  */
427 #define	XHCI_PORT_RZ	((1<<2) | (1<<24) | (0xf<<28))
428 
429 /**
430  * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable
431  * @state: u32 port value read from portsc register to be cleanup up
432  *
433  * Given a port state, this function returns a value that would result in the
434  * port being in the same state, if the value was written to the port status
435  * control register.
436  * Save Read Only (RO) bits and save read/write bits where
437  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
438  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
439  *
440  * Return: u32 value that can be written back to portsc register without
441  * changing port state.
442  */
443 
xhci_port_state_to_neutral(u32 state)444 u32 xhci_port_state_to_neutral(u32 state)
445 {
446 	/* Save read-only status and port state */
447 	return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
448 }
449 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral);
450 
451 /**
452  * xhci_find_slot_id_by_port() - Find slot id of a usb device on a roothub port
453  * @hcd: pointer to hcd of the roothub
454  * @xhci: pointer to xhci structure
455  * @port: one-based port number of the port in this roothub.
456  *
457  * Return: Slot id of the usb device connected to the root port, 0 if not found
458  */
459 
xhci_find_slot_id_by_port(struct usb_hcd * hcd,struct xhci_hcd * xhci,u16 port)460 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
461 		u16 port)
462 {
463 	int slot_id;
464 	int i;
465 	enum usb_device_speed speed;
466 
467 	slot_id = 0;
468 	for (i = 0; i < MAX_HC_SLOTS; i++) {
469 		if (!xhci->devs[i] || !xhci->devs[i]->udev)
470 			continue;
471 		speed = xhci->devs[i]->udev->speed;
472 		if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
473 				&& xhci->devs[i]->fake_port == port) {
474 			slot_id = i;
475 			break;
476 		}
477 	}
478 
479 	return slot_id;
480 }
481 EXPORT_SYMBOL_GPL(xhci_find_slot_id_by_port);
482 
483 /*
484  * Stop device
485  * It issues stop endpoint command for EP 0 to 30. And wait the last command
486  * to complete.
487  * suspend will set to 1, if suspend bit need to set in command.
488  */
xhci_stop_device(struct xhci_hcd * xhci,int slot_id,int suspend)489 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
490 {
491 	struct xhci_virt_device *virt_dev;
492 	struct xhci_command *cmd;
493 	unsigned long flags;
494 	int ret;
495 	int i;
496 
497 	ret = 0;
498 	virt_dev = xhci->devs[slot_id];
499 	if (!virt_dev)
500 		return -ENODEV;
501 
502 	trace_xhci_stop_device(virt_dev);
503 
504 	cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
505 	if (!cmd)
506 		return -ENOMEM;
507 
508 	spin_lock_irqsave(&xhci->lock, flags);
509 	for (i = LAST_EP_INDEX; i > 0; i--) {
510 		if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
511 			struct xhci_ep_ctx *ep_ctx;
512 			struct xhci_command *command;
513 
514 			ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
515 
516 			/* Check ep is running, required by AMD SNPS 3.1 xHC */
517 			if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
518 				continue;
519 
520 			command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
521 			if (!command) {
522 				spin_unlock_irqrestore(&xhci->lock, flags);
523 				ret = -ENOMEM;
524 				goto cmd_cleanup;
525 			}
526 
527 			ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
528 						       i, suspend);
529 			if (ret) {
530 				spin_unlock_irqrestore(&xhci->lock, flags);
531 				xhci_free_command(xhci, command);
532 				goto cmd_cleanup;
533 			}
534 		}
535 	}
536 	ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
537 	if (ret) {
538 		spin_unlock_irqrestore(&xhci->lock, flags);
539 		goto cmd_cleanup;
540 	}
541 
542 	xhci_ring_cmd_db(xhci);
543 	spin_unlock_irqrestore(&xhci->lock, flags);
544 
545 	/* Wait for last stop endpoint command to finish */
546 	wait_for_completion(cmd->completion);
547 
548 	if (cmd->status == COMP_COMMAND_ABORTED ||
549 	    cmd->status == COMP_COMMAND_RING_STOPPED) {
550 		xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
551 		ret = -ETIME;
552 	}
553 
554 cmd_cleanup:
555 	xhci_free_command(xhci, cmd);
556 	return ret;
557 }
558 
559 /*
560  * Ring device, it rings the all doorbells unconditionally.
561  */
xhci_ring_device(struct xhci_hcd * xhci,int slot_id)562 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
563 {
564 	int i, s;
565 	struct xhci_virt_ep *ep;
566 
567 	for (i = 0; i < LAST_EP_INDEX + 1; i++) {
568 		ep = &xhci->devs[slot_id]->eps[i];
569 
570 		if (ep->ep_state & EP_HAS_STREAMS) {
571 			for (s = 1; s < ep->stream_info->num_streams; s++)
572 				xhci_ring_ep_doorbell(xhci, slot_id, i, s);
573 		} else if (ep->ring && ep->ring->dequeue) {
574 			xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
575 		}
576 	}
577 
578 	return;
579 }
580 
xhci_disable_port(struct xhci_hcd * xhci,struct xhci_port * port)581 static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port)
582 {
583 	struct usb_hcd *hcd;
584 	u32 portsc;
585 
586 	hcd = port->rhub->hcd;
587 
588 	/* Don't allow the USB core to disable SuperSpeed ports. */
589 	if (hcd->speed >= HCD_USB3) {
590 		xhci_dbg(xhci, "Ignoring request to disable SuperSpeed port.\n");
591 		return;
592 	}
593 
594 	if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
595 		xhci_dbg(xhci,
596 			 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
597 		return;
598 	}
599 
600 	portsc = readl(port->addr);
601 	portsc = xhci_port_state_to_neutral(portsc);
602 
603 	/* Write 1 to disable the port */
604 	writel(portsc | PORT_PE, port->addr);
605 
606 	portsc = readl(port->addr);
607 	xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
608 		 hcd->self.busnum, port->hcd_portnum + 1, portsc);
609 }
610 
xhci_clear_port_change_bit(struct xhci_hcd * xhci,u16 wValue,u16 wIndex,__le32 __iomem * addr,u32 port_status)611 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
612 		u16 wIndex, __le32 __iomem *addr, u32 port_status)
613 {
614 	char *port_change_bit;
615 	u32 status;
616 
617 	switch (wValue) {
618 	case USB_PORT_FEAT_C_RESET:
619 		status = PORT_RC;
620 		port_change_bit = "reset";
621 		break;
622 	case USB_PORT_FEAT_C_BH_PORT_RESET:
623 		status = PORT_WRC;
624 		port_change_bit = "warm(BH) reset";
625 		break;
626 	case USB_PORT_FEAT_C_CONNECTION:
627 		status = PORT_CSC;
628 		port_change_bit = "connect";
629 		break;
630 	case USB_PORT_FEAT_C_OVER_CURRENT:
631 		status = PORT_OCC;
632 		port_change_bit = "over-current";
633 		break;
634 	case USB_PORT_FEAT_C_ENABLE:
635 		status = PORT_PEC;
636 		port_change_bit = "enable/disable";
637 		break;
638 	case USB_PORT_FEAT_C_SUSPEND:
639 		status = PORT_PLC;
640 		port_change_bit = "suspend/resume";
641 		break;
642 	case USB_PORT_FEAT_C_PORT_LINK_STATE:
643 		status = PORT_PLC;
644 		port_change_bit = "link state";
645 		break;
646 	case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
647 		status = PORT_CEC;
648 		port_change_bit = "config error";
649 		break;
650 	default:
651 		/* Should never happen */
652 		return;
653 	}
654 	/* Change bits are all write 1 to clear */
655 	writel(port_status | status, addr);
656 	port_status = readl(addr);
657 
658 	xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
659 		 wIndex + 1, port_change_bit, port_status);
660 }
661 
xhci_get_rhub(struct usb_hcd * hcd)662 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
663 {
664 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
665 
666 	if (hcd->speed >= HCD_USB3)
667 		return &xhci->usb3_rhub;
668 	return &xhci->usb2_rhub;
669 }
670 
671 /*
672  * xhci_set_port_power() must be called with xhci->lock held.
673  * It will release and re-aquire the lock while calling ACPI
674  * method.
675  */
xhci_set_port_power(struct xhci_hcd * xhci,struct xhci_port * port,bool on,unsigned long * flags)676 static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port,
677 				bool on, unsigned long *flags)
678 	__must_hold(&xhci->lock)
679 {
680 	struct usb_hcd *hcd;
681 	u32 temp;
682 
683 	hcd = port->rhub->hcd;
684 	temp = readl(port->addr);
685 
686 	xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
687 		 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp);
688 
689 	temp = xhci_port_state_to_neutral(temp);
690 
691 	if (on) {
692 		/* Power on */
693 		writel(temp | PORT_POWER, port->addr);
694 		readl(port->addr);
695 	} else {
696 		/* Power off */
697 		writel(temp & ~PORT_POWER, port->addr);
698 	}
699 
700 	spin_unlock_irqrestore(&xhci->lock, *flags);
701 	temp = usb_acpi_power_manageable(hcd->self.root_hub,
702 					 port->hcd_portnum);
703 	if (temp)
704 		usb_acpi_set_power_state(hcd->self.root_hub,
705 					 port->hcd_portnum, on);
706 	spin_lock_irqsave(&xhci->lock, *flags);
707 }
708 
xhci_port_set_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex)709 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
710 	u16 test_mode, u16 wIndex)
711 {
712 	u32 temp;
713 	struct xhci_port *port;
714 
715 	/* xhci only supports test mode for usb2 ports */
716 	port = xhci->usb2_rhub.ports[wIndex];
717 	temp = readl(port->addr + PORTPMSC);
718 	temp |= test_mode << PORT_TEST_MODE_SHIFT;
719 	writel(temp, port->addr + PORTPMSC);
720 	xhci->test_mode = test_mode;
721 	if (test_mode == USB_TEST_FORCE_ENABLE)
722 		xhci_start(xhci);
723 }
724 
xhci_enter_test_mode(struct xhci_hcd * xhci,u16 test_mode,u16 wIndex,unsigned long * flags)725 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
726 				u16 test_mode, u16 wIndex, unsigned long *flags)
727 	__must_hold(&xhci->lock)
728 {
729 	int i, retval;
730 
731 	/* Disable all Device Slots */
732 	xhci_dbg(xhci, "Disable all slots\n");
733 	spin_unlock_irqrestore(&xhci->lock, *flags);
734 	for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
735 		if (!xhci->devs[i])
736 			continue;
737 
738 		retval = xhci_disable_slot(xhci, i);
739 		xhci_free_virt_device(xhci, i);
740 		if (retval)
741 			xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
742 				 i, retval);
743 	}
744 	spin_lock_irqsave(&xhci->lock, *flags);
745 	/* Put all ports to the Disable state by clear PP */
746 	xhci_dbg(xhci, "Disable all port (PP = 0)\n");
747 	/* Power off USB3 ports*/
748 	for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
749 		xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags);
750 	/* Power off USB2 ports*/
751 	for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
752 		xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags);
753 	/* Stop the controller */
754 	xhci_dbg(xhci, "Stop controller\n");
755 	retval = xhci_halt(xhci);
756 	if (retval)
757 		return retval;
758 	/* Disable runtime PM for test mode */
759 	pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
760 	/* Set PORTPMSC.PTC field to enter selected test mode */
761 	/* Port is selected by wIndex. port_id = wIndex + 1 */
762 	xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
763 					test_mode, wIndex + 1);
764 	xhci_port_set_test_mode(xhci, test_mode, wIndex);
765 	return retval;
766 }
767 
xhci_exit_test_mode(struct xhci_hcd * xhci)768 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
769 {
770 	int retval;
771 
772 	if (!xhci->test_mode) {
773 		xhci_err(xhci, "Not in test mode, do nothing.\n");
774 		return 0;
775 	}
776 	if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
777 		!(xhci->xhc_state & XHCI_STATE_HALTED)) {
778 		retval = xhci_halt(xhci);
779 		if (retval)
780 			return retval;
781 	}
782 	pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
783 	xhci->test_mode = 0;
784 	return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
785 }
786 
xhci_set_link_state(struct xhci_hcd * xhci,struct xhci_port * port,u32 link_state)787 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
788 			 u32 link_state)
789 {
790 	u32 temp;
791 	u32 portsc;
792 
793 	portsc = readl(port->addr);
794 	temp = xhci_port_state_to_neutral(portsc);
795 	temp &= ~PORT_PLS_MASK;
796 	temp |= PORT_LINK_STROBE | link_state;
797 	writel(temp, port->addr);
798 
799 	xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
800 		 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
801 		 portsc, temp);
802 }
803 
xhci_set_remote_wake_mask(struct xhci_hcd * xhci,struct xhci_port * port,u16 wake_mask)804 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
805 				      struct xhci_port *port, u16 wake_mask)
806 {
807 	u32 temp;
808 
809 	temp = readl(port->addr);
810 	temp = xhci_port_state_to_neutral(temp);
811 
812 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
813 		temp |= PORT_WKCONN_E;
814 	else
815 		temp &= ~PORT_WKCONN_E;
816 
817 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
818 		temp |= PORT_WKDISC_E;
819 	else
820 		temp &= ~PORT_WKDISC_E;
821 
822 	if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
823 		temp |= PORT_WKOC_E;
824 	else
825 		temp &= ~PORT_WKOC_E;
826 
827 	writel(temp, port->addr);
828 }
829 
830 /* Test and clear port RWC bit */
xhci_test_and_clear_bit(struct xhci_hcd * xhci,struct xhci_port * port,u32 port_bit)831 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
832 			     u32 port_bit)
833 {
834 	u32 temp;
835 
836 	temp = readl(port->addr);
837 	if (temp & port_bit) {
838 		temp = xhci_port_state_to_neutral(temp);
839 		temp |= port_bit;
840 		writel(temp, port->addr);
841 	}
842 }
843 
844 /* Updates Link Status for super Speed port */
xhci_hub_report_usb3_link_state(struct xhci_hcd * xhci,u32 * status,u32 status_reg)845 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
846 		u32 *status, u32 status_reg)
847 {
848 	u32 pls = status_reg & PORT_PLS_MASK;
849 
850 	/* When the CAS bit is set then warm reset
851 	 * should be performed on port
852 	 */
853 	if (status_reg & PORT_CAS) {
854 		/* The CAS bit can be set while the port is
855 		 * in any link state.
856 		 * Only roothubs have CAS bit, so we
857 		 * pretend to be in compliance mode
858 		 * unless we're already in compliance
859 		 * or the inactive state.
860 		 */
861 		if (pls != USB_SS_PORT_LS_COMP_MOD &&
862 		    pls != USB_SS_PORT_LS_SS_INACTIVE) {
863 			pls = USB_SS_PORT_LS_COMP_MOD;
864 		}
865 		/* Return also connection bit -
866 		 * hub state machine resets port
867 		 * when this bit is set.
868 		 */
869 		pls |= USB_PORT_STAT_CONNECTION;
870 	} else {
871 		/*
872 		 * Resume state is an xHCI internal state.  Do not report it to
873 		 * usb core, instead, pretend to be U3, thus usb core knows
874 		 * it's not ready for transfer.
875 		 */
876 		if (pls == XDEV_RESUME) {
877 			*status |= USB_SS_PORT_LS_U3;
878 			return;
879 		}
880 
881 		/*
882 		 * If CAS bit isn't set but the Port is already at
883 		 * Compliance Mode, fake a connection so the USB core
884 		 * notices the Compliance state and resets the port.
885 		 * This resolves an issue generated by the SN65LVPE502CP
886 		 * in which sometimes the port enters compliance mode
887 		 * caused by a delay on the host-device negotiation.
888 		 */
889 		if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
890 				(pls == USB_SS_PORT_LS_COMP_MOD))
891 			pls |= USB_PORT_STAT_CONNECTION;
892 	}
893 
894 	/* update status field */
895 	*status |= pls;
896 }
897 
898 /*
899  * Function for Compliance Mode Quirk.
900  *
901  * This Function verifies if all xhc USB3 ports have entered U0, if so,
902  * the compliance mode timer is deleted. A port won't enter
903  * compliance mode if it has previously entered U0.
904  */
xhci_del_comp_mod_timer(struct xhci_hcd * xhci,u32 status,u16 wIndex)905 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
906 				    u16 wIndex)
907 {
908 	u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
909 	bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
910 
911 	if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
912 		return;
913 
914 	if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
915 		xhci->port_status_u0 |= 1 << wIndex;
916 		if (xhci->port_status_u0 == all_ports_seen_u0) {
917 			del_timer_sync(&xhci->comp_mode_recovery_timer);
918 			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
919 				"All USB3 ports have entered U0 already!");
920 			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
921 				"Compliance Mode Recovery Timer Deleted.");
922 		}
923 	}
924 }
925 
xhci_handle_usb2_port_link_resume(struct xhci_port * port,u32 portsc,unsigned long * flags)926 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
927 					     u32 portsc,
928 					     unsigned long *flags)
929 {
930 	struct xhci_bus_state *bus_state;
931 	struct xhci_hcd	*xhci;
932 	struct usb_hcd *hcd;
933 	int slot_id;
934 	u32 wIndex;
935 
936 	hcd = port->rhub->hcd;
937 	bus_state = &port->rhub->bus_state;
938 	xhci = hcd_to_xhci(hcd);
939 	wIndex = port->hcd_portnum;
940 
941 	if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
942 		return -EINVAL;
943 	}
944 	/* did port event handler already start resume timing? */
945 	if (!port->resume_timestamp) {
946 		/* If not, maybe we are in a host initated resume? */
947 		if (test_bit(wIndex, &bus_state->resuming_ports)) {
948 			/* Host initated resume doesn't time the resume
949 			 * signalling using resume_done[].
950 			 * It manually sets RESUME state, sleeps 20ms
951 			 * and sets U0 state. This should probably be
952 			 * changed, but not right now.
953 			 */
954 		} else {
955 			/* port resume was discovered now and here,
956 			 * start resume timing
957 			 */
958 			unsigned long timeout = jiffies +
959 				msecs_to_jiffies(USB_RESUME_TIMEOUT);
960 
961 			set_bit(wIndex, &bus_state->resuming_ports);
962 			port->resume_timestamp = timeout;
963 			mod_timer(&hcd->rh_timer, timeout);
964 			usb_hcd_start_port_resume(&hcd->self, wIndex);
965 		}
966 	/* Has resume been signalled for USB_RESUME_TIME yet? */
967 	} else if (time_after_eq(jiffies, port->resume_timestamp)) {
968 		int time_left;
969 
970 		xhci_dbg(xhci, "resume USB2 port %d-%d\n",
971 			 hcd->self.busnum, wIndex + 1);
972 
973 		port->resume_timestamp = 0;
974 		clear_bit(wIndex, &bus_state->resuming_ports);
975 
976 		reinit_completion(&port->rexit_done);
977 		port->rexit_active = true;
978 
979 		xhci_test_and_clear_bit(xhci, port, PORT_PLC);
980 		xhci_set_link_state(xhci, port, XDEV_U0);
981 
982 		spin_unlock_irqrestore(&xhci->lock, *flags);
983 		time_left = wait_for_completion_timeout(
984 			&port->rexit_done,
985 			msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
986 		spin_lock_irqsave(&xhci->lock, *flags);
987 
988 		if (time_left) {
989 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
990 							    wIndex + 1);
991 			if (!slot_id) {
992 				xhci_dbg(xhci, "slot_id is zero\n");
993 				return -ENODEV;
994 			}
995 			xhci_ring_device(xhci, slot_id);
996 		} else {
997 			int port_status = readl(port->addr);
998 
999 			xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
1000 				  hcd->self.busnum, wIndex + 1, port_status);
1001 			/*
1002 			 * keep rexit_active set if U0 transition failed so we
1003 			 * know to report PORT_STAT_SUSPEND status back to
1004 			 * usbcore. It will be cleared later once the port is
1005 			 * out of RESUME/U3 state
1006 			 */
1007 		}
1008 
1009 		usb_hcd_end_port_resume(&hcd->self, wIndex);
1010 		bus_state->port_c_suspend |= 1 << wIndex;
1011 		bus_state->suspended_ports &= ~(1 << wIndex);
1012 	}
1013 
1014 	return 0;
1015 }
1016 
xhci_get_ext_port_status(u32 raw_port_status,u32 port_li)1017 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
1018 {
1019 	u32 ext_stat = 0;
1020 	int speed_id;
1021 
1022 	/* only support rx and tx lane counts of 1 in usb3.1 spec */
1023 	speed_id = DEV_PORT_SPEED(raw_port_status);
1024 	ext_stat |= speed_id;		/* bits 3:0, RX speed id */
1025 	ext_stat |= speed_id << 4;	/* bits 7:4, TX speed id */
1026 
1027 	ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
1028 	ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
1029 
1030 	return ext_stat;
1031 }
1032 
xhci_get_usb3_port_status(struct xhci_port * port,u32 * status,u32 portsc)1033 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
1034 				      u32 portsc)
1035 {
1036 	struct xhci_bus_state *bus_state;
1037 	struct xhci_hcd	*xhci;
1038 	struct usb_hcd *hcd;
1039 	u32 link_state;
1040 	u32 portnum;
1041 
1042 	bus_state = &port->rhub->bus_state;
1043 	xhci = hcd_to_xhci(port->rhub->hcd);
1044 	hcd = port->rhub->hcd;
1045 	link_state = portsc & PORT_PLS_MASK;
1046 	portnum = port->hcd_portnum;
1047 
1048 	/* USB3 specific wPortChange bits
1049 	 *
1050 	 * Port link change with port in resume state should not be
1051 	 * reported to usbcore, as this is an internal state to be
1052 	 * handled by xhci driver. Reporting PLC to usbcore may
1053 	 * cause usbcore clearing PLC first and port change event
1054 	 * irq won't be generated.
1055 	 */
1056 
1057 	if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
1058 		*status |= USB_PORT_STAT_C_LINK_STATE << 16;
1059 	if (portsc & PORT_WRC)
1060 		*status |= USB_PORT_STAT_C_BH_RESET << 16;
1061 	if (portsc & PORT_CEC)
1062 		*status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
1063 
1064 	/* USB3 specific wPortStatus bits */
1065 	if (portsc & PORT_POWER)
1066 		*status |= USB_SS_PORT_STAT_POWER;
1067 
1068 	/* no longer suspended or resuming */
1069 	if (link_state != XDEV_U3 &&
1070 	    link_state != XDEV_RESUME &&
1071 	    link_state != XDEV_RECOVERY) {
1072 		/* remote wake resume signaling complete */
1073 		if (bus_state->port_remote_wakeup & (1 << portnum)) {
1074 			bus_state->port_remote_wakeup &= ~(1 << portnum);
1075 			usb_hcd_end_port_resume(&hcd->self, portnum);
1076 		}
1077 		bus_state->suspended_ports &= ~(1 << portnum);
1078 	}
1079 
1080 	xhci_hub_report_usb3_link_state(xhci, status, portsc);
1081 	xhci_del_comp_mod_timer(xhci, portsc, portnum);
1082 }
1083 
xhci_get_usb2_port_status(struct xhci_port * port,u32 * status,u32 portsc,unsigned long * flags)1084 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
1085 				      u32 portsc, unsigned long *flags)
1086 {
1087 	struct xhci_bus_state *bus_state;
1088 	u32 link_state;
1089 	u32 portnum;
1090 	int err;
1091 
1092 	bus_state = &port->rhub->bus_state;
1093 	link_state = portsc & PORT_PLS_MASK;
1094 	portnum = port->hcd_portnum;
1095 
1096 	/* USB2 wPortStatus bits */
1097 	if (portsc & PORT_POWER) {
1098 		*status |= USB_PORT_STAT_POWER;
1099 
1100 		/* link state is only valid if port is powered */
1101 		if (link_state == XDEV_U3)
1102 			*status |= USB_PORT_STAT_SUSPEND;
1103 		if (link_state == XDEV_U2)
1104 			*status |= USB_PORT_STAT_L1;
1105 		if (link_state == XDEV_U0) {
1106 			if (bus_state->suspended_ports & (1 << portnum)) {
1107 				bus_state->suspended_ports &= ~(1 << portnum);
1108 				bus_state->port_c_suspend |= 1 << portnum;
1109 			}
1110 		}
1111 		if (link_state == XDEV_RESUME) {
1112 			err = xhci_handle_usb2_port_link_resume(port, portsc,
1113 								flags);
1114 			if (err < 0)
1115 				*status = 0xffffffff;
1116 			else if (port->resume_timestamp || port->rexit_active)
1117 				*status |= USB_PORT_STAT_SUSPEND;
1118 		}
1119 	}
1120 
1121 	/*
1122 	 * Clear usb2 resume signalling variables if port is no longer suspended
1123 	 * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a
1124 	 * error state. Resume related variables should be cleared in all those cases.
1125 	 */
1126 	if (link_state != XDEV_U3 && link_state != XDEV_RESUME) {
1127 		if (port->resume_timestamp ||
1128 		    test_bit(portnum, &bus_state->resuming_ports)) {
1129 			port->resume_timestamp = 0;
1130 			clear_bit(portnum, &bus_state->resuming_ports);
1131 			usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum);
1132 		}
1133 		port->rexit_active = 0;
1134 		bus_state->suspended_ports &= ~(1 << portnum);
1135 	}
1136 }
1137 
1138 /*
1139  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1140  * 3.0 hubs use.
1141  *
1142  * Possible side effects:
1143  *  - Mark a port as being done with device resume,
1144  *    and ring the endpoint doorbells.
1145  *  - Stop the Synopsys redriver Compliance Mode polling.
1146  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1147  */
xhci_get_port_status(struct usb_hcd * hcd,struct xhci_bus_state * bus_state,u16 wIndex,u32 raw_port_status,unsigned long * flags)1148 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1149 		struct xhci_bus_state *bus_state,
1150 	u16 wIndex, u32 raw_port_status,
1151 		unsigned long *flags)
1152 	__releases(&xhci->lock)
1153 	__acquires(&xhci->lock)
1154 {
1155 	u32 status = 0;
1156 	struct xhci_hub *rhub;
1157 	struct xhci_port *port;
1158 
1159 	rhub = xhci_get_rhub(hcd);
1160 	port = rhub->ports[wIndex];
1161 
1162 	/* common wPortChange bits */
1163 	if (raw_port_status & PORT_CSC)
1164 		status |= USB_PORT_STAT_C_CONNECTION << 16;
1165 	if (raw_port_status & PORT_PEC)
1166 		status |= USB_PORT_STAT_C_ENABLE << 16;
1167 	if ((raw_port_status & PORT_OCC))
1168 		status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1169 	if ((raw_port_status & PORT_RC))
1170 		status |= USB_PORT_STAT_C_RESET << 16;
1171 
1172 	/* common wPortStatus bits */
1173 	if (raw_port_status & PORT_CONNECT) {
1174 		status |= USB_PORT_STAT_CONNECTION;
1175 		status |= xhci_port_speed(raw_port_status);
1176 	}
1177 	if (raw_port_status & PORT_PE)
1178 		status |= USB_PORT_STAT_ENABLE;
1179 	if (raw_port_status & PORT_OC)
1180 		status |= USB_PORT_STAT_OVERCURRENT;
1181 	if (raw_port_status & PORT_RESET)
1182 		status |= USB_PORT_STAT_RESET;
1183 
1184 	/* USB2 and USB3 specific bits, including Port Link State */
1185 	if (hcd->speed >= HCD_USB3)
1186 		xhci_get_usb3_port_status(port, &status, raw_port_status);
1187 	else
1188 		xhci_get_usb2_port_status(port, &status, raw_port_status,
1189 					  flags);
1190 
1191 	if (bus_state->port_c_suspend & (1 << wIndex))
1192 		status |= USB_PORT_STAT_C_SUSPEND << 16;
1193 
1194 	return status;
1195 }
1196 
xhci_hub_control(struct usb_hcd * hcd,u16 typeReq,u16 wValue,u16 wIndex,char * buf,u16 wLength)1197 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1198 		u16 wIndex, char *buf, u16 wLength)
1199 {
1200 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1201 	int max_ports;
1202 	unsigned long flags;
1203 	u32 temp, status;
1204 	int retval = 0;
1205 	int slot_id;
1206 	struct xhci_bus_state *bus_state;
1207 	u16 link_state = 0;
1208 	u16 wake_mask = 0;
1209 	u16 timeout = 0;
1210 	u16 test_mode = 0;
1211 	struct xhci_hub *rhub;
1212 	struct xhci_port **ports;
1213 	struct xhci_port *port;
1214 	int portnum1;
1215 
1216 	rhub = xhci_get_rhub(hcd);
1217 	ports = rhub->ports;
1218 	max_ports = rhub->num_ports;
1219 	bus_state = &rhub->bus_state;
1220 	portnum1 = wIndex & 0xff;
1221 
1222 	spin_lock_irqsave(&xhci->lock, flags);
1223 	switch (typeReq) {
1224 	case GetHubStatus:
1225 		/* No power source, over-current reported per port */
1226 		memset(buf, 0, 4);
1227 		break;
1228 	case GetHubDescriptor:
1229 		/* Check to make sure userspace is asking for the USB 3.0 hub
1230 		 * descriptor for the USB 3.0 roothub.  If not, we stall the
1231 		 * endpoint, like external hubs do.
1232 		 */
1233 		if (hcd->speed >= HCD_USB3 &&
1234 				(wLength < USB_DT_SS_HUB_SIZE ||
1235 				 wValue != (USB_DT_SS_HUB << 8))) {
1236 			xhci_dbg(xhci, "Wrong hub descriptor type for "
1237 					"USB 3.0 roothub.\n");
1238 			goto error;
1239 		}
1240 		xhci_hub_descriptor(hcd, xhci,
1241 				(struct usb_hub_descriptor *) buf);
1242 		break;
1243 	case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1244 		if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1245 			goto error;
1246 
1247 		if (hcd->speed < HCD_USB3)
1248 			goto error;
1249 
1250 		retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength);
1251 		spin_unlock_irqrestore(&xhci->lock, flags);
1252 		return retval;
1253 	case GetPortStatus:
1254 		if (!portnum1 || portnum1 > max_ports)
1255 			goto error;
1256 
1257 		wIndex--;
1258 		port = ports[portnum1 - 1];
1259 		temp = readl(port->addr);
1260 		if (temp == ~(u32)0) {
1261 			xhci_hc_died(xhci);
1262 			retval = -ENODEV;
1263 			break;
1264 		}
1265 		trace_xhci_get_port_status(wIndex, temp);
1266 		status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1267 					      &flags);
1268 		if (status == 0xffffffff)
1269 			goto error;
1270 
1271 		xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1272 			 hcd->self.busnum, portnum1, temp, status);
1273 
1274 		put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1275 		/* if USB 3.1 extended port status return additional 4 bytes */
1276 		if (wValue == 0x02) {
1277 			u32 port_li;
1278 
1279 			if (hcd->speed < HCD_USB31 || wLength != 8) {
1280 				xhci_err(xhci, "get ext port status invalid parameter\n");
1281 				retval = -EINVAL;
1282 				break;
1283 			}
1284 			port_li = readl(port->addr + PORTLI);
1285 			status = xhci_get_ext_port_status(temp, port_li);
1286 			put_unaligned_le32(status, &buf[4]);
1287 		}
1288 		break;
1289 	case SetPortFeature:
1290 		if (wValue == USB_PORT_FEAT_LINK_STATE)
1291 			link_state = (wIndex & 0xff00) >> 3;
1292 		if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1293 			wake_mask = wIndex & 0xff00;
1294 		if (wValue == USB_PORT_FEAT_TEST)
1295 			test_mode = (wIndex & 0xff00) >> 8;
1296 		/* The MSB of wIndex is the U1/U2 timeout */
1297 		timeout = (wIndex & 0xff00) >> 8;
1298 
1299 		wIndex &= 0xff;
1300 		if (!portnum1 || portnum1 > max_ports)
1301 			goto error;
1302 
1303 		port = ports[portnum1 - 1];
1304 		wIndex--;
1305 		temp = readl(port->addr);
1306 		if (temp == ~(u32)0) {
1307 			xhci_hc_died(xhci);
1308 			retval = -ENODEV;
1309 			break;
1310 		}
1311 		temp = xhci_port_state_to_neutral(temp);
1312 		/* FIXME: What new port features do we need to support? */
1313 		switch (wValue) {
1314 		case USB_PORT_FEAT_SUSPEND:
1315 			temp = readl(port->addr);
1316 			if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1317 				/* Resume the port to U0 first */
1318 				xhci_set_link_state(xhci, port, XDEV_U0);
1319 				spin_unlock_irqrestore(&xhci->lock, flags);
1320 				msleep(10);
1321 				spin_lock_irqsave(&xhci->lock, flags);
1322 			}
1323 			/* In spec software should not attempt to suspend
1324 			 * a port unless the port reports that it is in the
1325 			 * enabled (PED = ‘1’,PLS < ‘3’) state.
1326 			 */
1327 			temp = readl(port->addr);
1328 			if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1329 				|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
1330 				xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1331 					  hcd->self.busnum, portnum1);
1332 				goto error;
1333 			}
1334 
1335 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1336 							    portnum1);
1337 			if (!slot_id) {
1338 				xhci_warn(xhci, "slot_id is zero\n");
1339 				goto error;
1340 			}
1341 			/* unlock to execute stop endpoint commands */
1342 			spin_unlock_irqrestore(&xhci->lock, flags);
1343 			xhci_stop_device(xhci, slot_id, 1);
1344 			spin_lock_irqsave(&xhci->lock, flags);
1345 
1346 			xhci_set_link_state(xhci, port, XDEV_U3);
1347 
1348 			spin_unlock_irqrestore(&xhci->lock, flags);
1349 			msleep(10); /* wait device to enter */
1350 			spin_lock_irqsave(&xhci->lock, flags);
1351 
1352 			temp = readl(port->addr);
1353 			bus_state->suspended_ports |= 1 << wIndex;
1354 			break;
1355 		case USB_PORT_FEAT_LINK_STATE:
1356 			temp = readl(port->addr);
1357 			/* Disable port */
1358 			if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1359 				xhci_dbg(xhci, "Disable port %d-%d\n",
1360 					 hcd->self.busnum, portnum1);
1361 				temp = xhci_port_state_to_neutral(temp);
1362 				/*
1363 				 * Clear all change bits, so that we get a new
1364 				 * connection event.
1365 				 */
1366 				temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1367 					PORT_OCC | PORT_RC | PORT_PLC |
1368 					PORT_CEC;
1369 				writel(temp | PORT_PE, port->addr);
1370 				temp = readl(port->addr);
1371 				break;
1372 			}
1373 
1374 			/* Put link in RxDetect (enable port) */
1375 			if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1376 				xhci_dbg(xhci, "Enable port %d-%d\n",
1377 					 hcd->self.busnum, portnum1);
1378 				xhci_set_link_state(xhci, port,	link_state);
1379 				temp = readl(port->addr);
1380 				break;
1381 			}
1382 
1383 			/*
1384 			 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1385 			 * root hub port's transition to compliance mode upon
1386 			 * detecting LFPS timeout may be controlled by an
1387 			 * Compliance Transition Enabled (CTE) flag (not
1388 			 * software visible). This flag is set by writing 0xA
1389 			 * to PORTSC PLS field which will allow transition to
1390 			 * compliance mode the next time LFPS timeout is
1391 			 * encountered. A warm reset will clear it.
1392 			 *
1393 			 * The CTE flag is only supported if the HCCPARAMS2 CTC
1394 			 * flag is set, otherwise, the compliance substate is
1395 			 * automatically entered as on 1.0 and prior.
1396 			 */
1397 			if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1398 				if (!HCC2_CTC(xhci->hcc_params2)) {
1399 					xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1400 					break;
1401 				}
1402 
1403 				if ((temp & PORT_CONNECT)) {
1404 					xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1405 					goto error;
1406 				}
1407 
1408 				xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1409 					 hcd->self.busnum, portnum1);
1410 				xhci_set_link_state(xhci, port, link_state);
1411 
1412 				temp = readl(port->addr);
1413 				break;
1414 			}
1415 			/* Port must be enabled */
1416 			if (!(temp & PORT_PE)) {
1417 				retval = -ENODEV;
1418 				break;
1419 			}
1420 			/* Can't set port link state above '3' (U3) */
1421 			if (link_state > USB_SS_PORT_LS_U3) {
1422 				xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1423 					  hcd->self.busnum, portnum1, link_state);
1424 				goto error;
1425 			}
1426 
1427 			/*
1428 			 * set link to U0, steps depend on current link state.
1429 			 * U3: set link to U0 and wait for u3exit completion.
1430 			 * U1/U2:  no PLC complete event, only set link to U0.
1431 			 * Resume/Recovery: device initiated U0, only wait for
1432 			 * completion
1433 			 */
1434 			if (link_state == USB_SS_PORT_LS_U0) {
1435 				u32 pls = temp & PORT_PLS_MASK;
1436 				bool wait_u0 = false;
1437 
1438 				/* already in U0 */
1439 				if (pls == XDEV_U0)
1440 					break;
1441 				if (pls == XDEV_U3 ||
1442 				    pls == XDEV_RESUME ||
1443 				    pls == XDEV_RECOVERY) {
1444 					wait_u0 = true;
1445 					reinit_completion(&port->u3exit_done);
1446 				}
1447 				if (pls <= XDEV_U3) /* U1, U2, U3 */
1448 					xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0);
1449 				if (!wait_u0) {
1450 					if (pls > XDEV_U3)
1451 						goto error;
1452 					break;
1453 				}
1454 				spin_unlock_irqrestore(&xhci->lock, flags);
1455 				if (!wait_for_completion_timeout(&port->u3exit_done,
1456 								 msecs_to_jiffies(500)))
1457 					xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1458 						 hcd->self.busnum, portnum1);
1459 				spin_lock_irqsave(&xhci->lock, flags);
1460 				temp = readl(port->addr);
1461 				break;
1462 			}
1463 
1464 			if (link_state == USB_SS_PORT_LS_U3) {
1465 				int retries = 16;
1466 				slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1467 								    portnum1);
1468 				if (slot_id) {
1469 					/* unlock to execute stop endpoint
1470 					 * commands */
1471 					spin_unlock_irqrestore(&xhci->lock,
1472 								flags);
1473 					xhci_stop_device(xhci, slot_id, 1);
1474 					spin_lock_irqsave(&xhci->lock, flags);
1475 				}
1476 				xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3);
1477 				spin_unlock_irqrestore(&xhci->lock, flags);
1478 				while (retries--) {
1479 					usleep_range(4000, 8000);
1480 					temp = readl(port->addr);
1481 					if ((temp & PORT_PLS_MASK) == XDEV_U3)
1482 						break;
1483 				}
1484 				spin_lock_irqsave(&xhci->lock, flags);
1485 				temp = readl(port->addr);
1486 				bus_state->suspended_ports |= 1 << wIndex;
1487 			}
1488 			break;
1489 		case USB_PORT_FEAT_POWER:
1490 			/*
1491 			 * Turn on ports, even if there isn't per-port switching.
1492 			 * HC will report connect events even before this is set.
1493 			 * However, hub_wq will ignore the roothub events until
1494 			 * the roothub is registered.
1495 			 */
1496 			xhci_set_port_power(xhci, port, true, &flags);
1497 			break;
1498 		case USB_PORT_FEAT_RESET:
1499 			temp = (temp | PORT_RESET);
1500 			writel(temp, port->addr);
1501 
1502 			temp = readl(port->addr);
1503 			xhci_dbg(xhci, "set port reset, actual port %d-%d status  = 0x%x\n",
1504 				 hcd->self.busnum, portnum1, temp);
1505 			break;
1506 		case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1507 			xhci_set_remote_wake_mask(xhci, port, wake_mask);
1508 			temp = readl(port->addr);
1509 			xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status  = 0x%x\n",
1510 				 hcd->self.busnum, portnum1, temp);
1511 			break;
1512 		case USB_PORT_FEAT_BH_PORT_RESET:
1513 			temp |= PORT_WR;
1514 			writel(temp, port->addr);
1515 			temp = readl(port->addr);
1516 			break;
1517 		case USB_PORT_FEAT_U1_TIMEOUT:
1518 			if (hcd->speed < HCD_USB3)
1519 				goto error;
1520 			temp = readl(port->addr + PORTPMSC);
1521 			temp &= ~PORT_U1_TIMEOUT_MASK;
1522 			temp |= PORT_U1_TIMEOUT(timeout);
1523 			writel(temp, port->addr + PORTPMSC);
1524 			break;
1525 		case USB_PORT_FEAT_U2_TIMEOUT:
1526 			if (hcd->speed < HCD_USB3)
1527 				goto error;
1528 			temp = readl(port->addr + PORTPMSC);
1529 			temp &= ~PORT_U2_TIMEOUT_MASK;
1530 			temp |= PORT_U2_TIMEOUT(timeout);
1531 			writel(temp, port->addr + PORTPMSC);
1532 			break;
1533 		case USB_PORT_FEAT_TEST:
1534 			/* 4.19.6 Port Test Modes (USB2 Test Mode) */
1535 			if (hcd->speed != HCD_USB2)
1536 				goto error;
1537 			if (test_mode > USB_TEST_FORCE_ENABLE ||
1538 			    test_mode < USB_TEST_J)
1539 				goto error;
1540 			retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1541 						      &flags);
1542 			break;
1543 		default:
1544 			goto error;
1545 		}
1546 		/* unblock any posted writes */
1547 		temp = readl(port->addr);
1548 		break;
1549 	case ClearPortFeature:
1550 		if (!portnum1 || portnum1 > max_ports)
1551 			goto error;
1552 
1553 		port = ports[portnum1 - 1];
1554 
1555 		wIndex--;
1556 		temp = readl(port->addr);
1557 		if (temp == ~(u32)0) {
1558 			xhci_hc_died(xhci);
1559 			retval = -ENODEV;
1560 			break;
1561 		}
1562 		/* FIXME: What new port features do we need to support? */
1563 		temp = xhci_port_state_to_neutral(temp);
1564 		switch (wValue) {
1565 		case USB_PORT_FEAT_SUSPEND:
1566 			temp = readl(port->addr);
1567 			xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1568 			xhci_dbg(xhci, "PORTSC %04x\n", temp);
1569 			if (temp & PORT_RESET)
1570 				goto error;
1571 			if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1572 				if ((temp & PORT_PE) == 0)
1573 					goto error;
1574 
1575 				set_bit(wIndex, &bus_state->resuming_ports);
1576 				usb_hcd_start_port_resume(&hcd->self, wIndex);
1577 				xhci_set_link_state(xhci, port, XDEV_RESUME);
1578 				spin_unlock_irqrestore(&xhci->lock, flags);
1579 				msleep(USB_RESUME_TIMEOUT);
1580 				spin_lock_irqsave(&xhci->lock, flags);
1581 				xhci_set_link_state(xhci, port, XDEV_U0);
1582 				clear_bit(wIndex, &bus_state->resuming_ports);
1583 				usb_hcd_end_port_resume(&hcd->self, wIndex);
1584 			}
1585 			bus_state->port_c_suspend |= 1 << wIndex;
1586 
1587 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1588 					portnum1);
1589 			if (!slot_id) {
1590 				xhci_dbg(xhci, "slot_id is zero\n");
1591 				goto error;
1592 			}
1593 			xhci_ring_device(xhci, slot_id);
1594 			break;
1595 		case USB_PORT_FEAT_C_SUSPEND:
1596 			bus_state->port_c_suspend &= ~(1 << wIndex);
1597 			fallthrough;
1598 		case USB_PORT_FEAT_C_RESET:
1599 		case USB_PORT_FEAT_C_BH_PORT_RESET:
1600 		case USB_PORT_FEAT_C_CONNECTION:
1601 		case USB_PORT_FEAT_C_OVER_CURRENT:
1602 		case USB_PORT_FEAT_C_ENABLE:
1603 		case USB_PORT_FEAT_C_PORT_LINK_STATE:
1604 		case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1605 			xhci_clear_port_change_bit(xhci, wValue, wIndex,
1606 					port->addr, temp);
1607 			break;
1608 		case USB_PORT_FEAT_ENABLE:
1609 			xhci_disable_port(xhci, port);
1610 			break;
1611 		case USB_PORT_FEAT_POWER:
1612 			xhci_set_port_power(xhci, port, false, &flags);
1613 			break;
1614 		case USB_PORT_FEAT_TEST:
1615 			retval = xhci_exit_test_mode(xhci);
1616 			break;
1617 		default:
1618 			goto error;
1619 		}
1620 		break;
1621 	default:
1622 error:
1623 		/* "stall" on error */
1624 		retval = -EPIPE;
1625 	}
1626 	spin_unlock_irqrestore(&xhci->lock, flags);
1627 	return retval;
1628 }
1629 EXPORT_SYMBOL_GPL(xhci_hub_control);
1630 
1631 /*
1632  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1633  * Ports are 0-indexed from the HCD point of view,
1634  * and 1-indexed from the USB core pointer of view.
1635  *
1636  * Note that the status change bits will be cleared as soon as a port status
1637  * change event is generated, so we use the saved status from that event.
1638  */
xhci_hub_status_data(struct usb_hcd * hcd,char * buf)1639 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1640 {
1641 	unsigned long flags;
1642 	u32 temp, status;
1643 	u32 mask;
1644 	int i, retval;
1645 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1646 	int max_ports;
1647 	struct xhci_bus_state *bus_state;
1648 	bool reset_change = false;
1649 	struct xhci_hub *rhub;
1650 	struct xhci_port **ports;
1651 
1652 	rhub = xhci_get_rhub(hcd);
1653 	ports = rhub->ports;
1654 	max_ports = rhub->num_ports;
1655 	bus_state = &rhub->bus_state;
1656 
1657 	/* Initial status is no changes */
1658 	retval = (max_ports + 8) / 8;
1659 	memset(buf, 0, retval);
1660 
1661 	/*
1662 	 * Inform the usbcore about resume-in-progress by returning
1663 	 * a non-zero value even if there are no status changes.
1664 	 */
1665 	spin_lock_irqsave(&xhci->lock, flags);
1666 
1667 	status = bus_state->resuming_ports;
1668 
1669 	/*
1670 	 * SS devices are only visible to roothub after link training completes.
1671 	 * Keep polling roothubs for a grace period after xHC start
1672 	 */
1673 	if (xhci->run_graceperiod) {
1674 		if (time_before(jiffies, xhci->run_graceperiod))
1675 			status = 1;
1676 		else
1677 			xhci->run_graceperiod = 0;
1678 	}
1679 
1680 	mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1681 
1682 	/* For each port, did anything change?  If so, set that bit in buf. */
1683 	for (i = 0; i < max_ports; i++) {
1684 		temp = readl(ports[i]->addr);
1685 		if (temp == ~(u32)0) {
1686 			xhci_hc_died(xhci);
1687 			retval = -ENODEV;
1688 			break;
1689 		}
1690 		trace_xhci_hub_status_data(i, temp);
1691 
1692 		if ((temp & mask) != 0 ||
1693 			(bus_state->port_c_suspend & 1 << i) ||
1694 			(ports[i]->resume_timestamp && time_after_eq(
1695 			    jiffies, ports[i]->resume_timestamp))) {
1696 			buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1697 			status = 1;
1698 		}
1699 		if ((temp & PORT_RC))
1700 			reset_change = true;
1701 		if (temp & PORT_OC)
1702 			status = 1;
1703 	}
1704 	if (!status && !reset_change) {
1705 		xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
1706 			 __func__, hcd->self.busnum);
1707 		clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1708 	}
1709 	spin_unlock_irqrestore(&xhci->lock, flags);
1710 	return status ? retval : 0;
1711 }
1712 
1713 #ifdef CONFIG_PM
1714 
xhci_bus_suspend(struct usb_hcd * hcd)1715 int xhci_bus_suspend(struct usb_hcd *hcd)
1716 {
1717 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1718 	int max_ports, port_index;
1719 	struct xhci_bus_state *bus_state;
1720 	unsigned long flags;
1721 	struct xhci_hub *rhub;
1722 	struct xhci_port **ports;
1723 	u32 portsc_buf[USB_MAXCHILDREN];
1724 	bool wake_enabled;
1725 
1726 	rhub = xhci_get_rhub(hcd);
1727 	ports = rhub->ports;
1728 	max_ports = rhub->num_ports;
1729 	bus_state = &rhub->bus_state;
1730 	wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1731 
1732 	spin_lock_irqsave(&xhci->lock, flags);
1733 
1734 	if (wake_enabled) {
1735 		if (bus_state->resuming_ports ||	/* USB2 */
1736 		    bus_state->port_remote_wakeup) {	/* USB3 */
1737 			spin_unlock_irqrestore(&xhci->lock, flags);
1738 			xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
1739 				 hcd->self.busnum);
1740 			return -EBUSY;
1741 		}
1742 	}
1743 	/*
1744 	 * Prepare ports for suspend, but don't write anything before all ports
1745 	 * are checked and we know bus suspend can proceed
1746 	 */
1747 	bus_state->bus_suspended = 0;
1748 	port_index = max_ports;
1749 	while (port_index--) {
1750 		u32 t1, t2;
1751 		int retries = 10;
1752 retry:
1753 		t1 = readl(ports[port_index]->addr);
1754 		t2 = xhci_port_state_to_neutral(t1);
1755 		portsc_buf[port_index] = 0;
1756 
1757 		/*
1758 		 * Give a USB3 port in link training time to finish, but don't
1759 		 * prevent suspend as port might be stuck
1760 		 */
1761 		if ((hcd->speed >= HCD_USB3) && retries-- &&
1762 		    (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1763 			spin_unlock_irqrestore(&xhci->lock, flags);
1764 			msleep(XHCI_PORT_POLLING_LFPS_TIME);
1765 			spin_lock_irqsave(&xhci->lock, flags);
1766 			xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1767 				 hcd->self.busnum, port_index + 1);
1768 			goto retry;
1769 		}
1770 		/* bail out if port detected a over-current condition */
1771 		if (t1 & PORT_OC) {
1772 			bus_state->bus_suspended = 0;
1773 			spin_unlock_irqrestore(&xhci->lock, flags);
1774 			xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1775 			return -EBUSY;
1776 		}
1777 		/* suspend ports in U0, or bail out for new connect changes */
1778 		if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1779 			if ((t1 & PORT_CSC) && wake_enabled) {
1780 				bus_state->bus_suspended = 0;
1781 				spin_unlock_irqrestore(&xhci->lock, flags);
1782 				xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1783 				return -EBUSY;
1784 			}
1785 			xhci_dbg(xhci, "port %d-%d not suspended\n",
1786 				 hcd->self.busnum, port_index + 1);
1787 			t2 &= ~PORT_PLS_MASK;
1788 			t2 |= PORT_LINK_STROBE | XDEV_U3;
1789 			set_bit(port_index, &bus_state->bus_suspended);
1790 		}
1791 		/* USB core sets remote wake mask for USB 3.0 hubs,
1792 		 * including the USB 3.0 roothub, but only if CONFIG_PM
1793 		 * is enabled, so also enable remote wake here.
1794 		 */
1795 		if (wake_enabled) {
1796 			if (t1 & PORT_CONNECT) {
1797 				t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1798 				t2 &= ~PORT_WKCONN_E;
1799 			} else {
1800 				t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1801 				t2 &= ~PORT_WKDISC_E;
1802 			}
1803 
1804 			if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1805 			    (hcd->speed < HCD_USB3)) {
1806 				if (usb_amd_pt_check_port(hcd->self.controller,
1807 							  port_index))
1808 					t2 &= ~PORT_WAKE_BITS;
1809 			}
1810 		} else
1811 			t2 &= ~PORT_WAKE_BITS;
1812 
1813 		t1 = xhci_port_state_to_neutral(t1);
1814 		if (t1 != t2)
1815 			portsc_buf[port_index] = t2;
1816 	}
1817 
1818 	/* write port settings, stopping and suspending ports if needed */
1819 	port_index = max_ports;
1820 	while (port_index--) {
1821 		if (!portsc_buf[port_index])
1822 			continue;
1823 		if (test_bit(port_index, &bus_state->bus_suspended)) {
1824 			int slot_id;
1825 
1826 			slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1827 							    port_index + 1);
1828 			if (slot_id) {
1829 				spin_unlock_irqrestore(&xhci->lock, flags);
1830 				xhci_stop_device(xhci, slot_id, 1);
1831 				spin_lock_irqsave(&xhci->lock, flags);
1832 			}
1833 		}
1834 		writel(portsc_buf[port_index], ports[port_index]->addr);
1835 	}
1836 	hcd->state = HC_STATE_SUSPENDED;
1837 	bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1838 	spin_unlock_irqrestore(&xhci->lock, flags);
1839 
1840 	if (bus_state->bus_suspended)
1841 		usleep_range(5000, 10000);
1842 
1843 	return 0;
1844 }
1845 
1846 /*
1847  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1848  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1849  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1850  */
xhci_port_missing_cas_quirk(struct xhci_port * port)1851 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1852 {
1853 	u32 portsc;
1854 
1855 	portsc = readl(port->addr);
1856 
1857 	/* if any of these are set we are not stuck */
1858 	if (portsc & (PORT_CONNECT | PORT_CAS))
1859 		return false;
1860 
1861 	if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1862 	    ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1863 		return false;
1864 
1865 	/* clear wakeup/change bits, and do a warm port reset */
1866 	portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1867 	portsc |= PORT_WR;
1868 	writel(portsc, port->addr);
1869 	/* flush write */
1870 	readl(port->addr);
1871 	return true;
1872 }
1873 
xhci_bus_resume(struct usb_hcd * hcd)1874 int xhci_bus_resume(struct usb_hcd *hcd)
1875 {
1876 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
1877 	struct xhci_bus_state *bus_state;
1878 	unsigned long flags;
1879 	int max_ports, port_index;
1880 	int slot_id;
1881 	int sret;
1882 	u32 next_state;
1883 	u32 temp, portsc;
1884 	struct xhci_hub *rhub;
1885 	struct xhci_port **ports;
1886 
1887 	rhub = xhci_get_rhub(hcd);
1888 	ports = rhub->ports;
1889 	max_ports = rhub->num_ports;
1890 	bus_state = &rhub->bus_state;
1891 
1892 	if (time_before(jiffies, bus_state->next_statechange))
1893 		msleep(5);
1894 
1895 	spin_lock_irqsave(&xhci->lock, flags);
1896 	if (!HCD_HW_ACCESSIBLE(hcd)) {
1897 		spin_unlock_irqrestore(&xhci->lock, flags);
1898 		return -ESHUTDOWN;
1899 	}
1900 
1901 	/* delay the irqs */
1902 	temp = readl(&xhci->op_regs->command);
1903 	temp &= ~CMD_EIE;
1904 	writel(temp, &xhci->op_regs->command);
1905 
1906 	/* bus specific resume for ports we suspended at bus_suspend */
1907 	if (hcd->speed >= HCD_USB3)
1908 		next_state = XDEV_U0;
1909 	else
1910 		next_state = XDEV_RESUME;
1911 
1912 	port_index = max_ports;
1913 	while (port_index--) {
1914 		portsc = readl(ports[port_index]->addr);
1915 
1916 		/* warm reset CAS limited ports stuck in polling/compliance */
1917 		if ((xhci->quirks & XHCI_MISSING_CAS) &&
1918 		    (hcd->speed >= HCD_USB3) &&
1919 		    xhci_port_missing_cas_quirk(ports[port_index])) {
1920 			xhci_dbg(xhci, "reset stuck port %d-%d\n",
1921 				 hcd->self.busnum, port_index + 1);
1922 			clear_bit(port_index, &bus_state->bus_suspended);
1923 			continue;
1924 		}
1925 		/* resume if we suspended the link, and it is still suspended */
1926 		if (test_bit(port_index, &bus_state->bus_suspended))
1927 			switch (portsc & PORT_PLS_MASK) {
1928 			case XDEV_U3:
1929 				portsc = xhci_port_state_to_neutral(portsc);
1930 				portsc &= ~PORT_PLS_MASK;
1931 				portsc |= PORT_LINK_STROBE | next_state;
1932 				break;
1933 			case XDEV_RESUME:
1934 				/* resume already initiated */
1935 				break;
1936 			default:
1937 				/* not in a resumeable state, ignore it */
1938 				clear_bit(port_index,
1939 					  &bus_state->bus_suspended);
1940 				break;
1941 			}
1942 		/* disable wake for all ports, write new link state if needed */
1943 		portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1944 		writel(portsc, ports[port_index]->addr);
1945 	}
1946 
1947 	/* USB2 specific resume signaling delay and U0 link state transition */
1948 	if (hcd->speed < HCD_USB3) {
1949 		if (bus_state->bus_suspended) {
1950 			spin_unlock_irqrestore(&xhci->lock, flags);
1951 			msleep(USB_RESUME_TIMEOUT);
1952 			spin_lock_irqsave(&xhci->lock, flags);
1953 		}
1954 		for_each_set_bit(port_index, &bus_state->bus_suspended,
1955 				 BITS_PER_LONG) {
1956 			/* Clear PLC to poll it later for U0 transition */
1957 			xhci_test_and_clear_bit(xhci, ports[port_index],
1958 						PORT_PLC);
1959 			xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1960 		}
1961 	}
1962 
1963 	/* poll for U0 link state complete, both USB2 and USB3 */
1964 	for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1965 		sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1966 				      PORT_PLC, 10 * 1000);
1967 		if (sret) {
1968 			xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1969 				  hcd->self.busnum, port_index + 1);
1970 			continue;
1971 		}
1972 		xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1973 		slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1974 		if (slot_id)
1975 			xhci_ring_device(xhci, slot_id);
1976 	}
1977 	(void) readl(&xhci->op_regs->command);
1978 
1979 	bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1980 	/* re-enable irqs */
1981 	temp = readl(&xhci->op_regs->command);
1982 	temp |= CMD_EIE;
1983 	writel(temp, &xhci->op_regs->command);
1984 	temp = readl(&xhci->op_regs->command);
1985 
1986 	spin_unlock_irqrestore(&xhci->lock, flags);
1987 	return 0;
1988 }
1989 
xhci_get_resuming_ports(struct usb_hcd * hcd)1990 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1991 {
1992 	struct xhci_hub *rhub = xhci_get_rhub(hcd);
1993 
1994 	/* USB3 port wakeups are reported via usb_wakeup_notification() */
1995 	return rhub->bus_state.resuming_ports;	/* USB2 ports only */
1996 }
1997 
1998 #endif	/* CONFIG_PM */
1999