xref: /openbmc/linux/drivers/gpio/gpio-xilinx.c (revision e91d0f05)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Xilinx gpio driver for xps/axi_gpio IP.
4  *
5  * Copyright 2008 - 2013 Xilinx, Inc.
6  */
7 
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/slab.h>
22 
23 /* Register Offset Definitions */
24 #define XGPIO_DATA_OFFSET   (0x0)	/* Data register  */
25 #define XGPIO_TRI_OFFSET    (0x4)	/* I/O direction register  */
26 
27 #define XGPIO_CHANNEL0_OFFSET	0x0
28 #define XGPIO_CHANNEL1_OFFSET	0x8
29 
30 #define XGPIO_GIER_OFFSET	0x11c /* Global Interrupt Enable */
31 #define XGPIO_GIER_IE		BIT(31)
32 #define XGPIO_IPISR_OFFSET	0x120 /* IP Interrupt Status */
33 #define XGPIO_IPIER_OFFSET	0x128 /* IP Interrupt Enable */
34 
35 /* Read/Write access to the GPIO registers */
36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37 # define xgpio_readreg(offset)		readl(offset)
38 # define xgpio_writereg(offset, val)	writel(val, offset)
39 #else
40 # define xgpio_readreg(offset)		__raw_readl(offset)
41 # define xgpio_writereg(offset, val)	__raw_writel(val, offset)
42 #endif
43 
44 /**
45  * struct xgpio_instance - Stores information about GPIO device
46  * @gc: GPIO chip
47  * @regs: register block
48  * @hw_map: GPIO pin mapping on hardware side
49  * @sw_map: GPIO pin mapping on software side
50  * @state: GPIO write state shadow register
51  * @last_irq_read: GPIO read state register from last interrupt
52  * @dir: GPIO direction shadow register
53  * @gpio_lock: Lock used for synchronization
54  * @irq: IRQ used by GPIO device
55  * @irqchip: IRQ chip
56  * @enable: GPIO IRQ enable/disable bitfield
57  * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
58  * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
59  * @clk: clock resource for this driver
60  */
61 struct xgpio_instance {
62 	struct gpio_chip gc;
63 	void __iomem *regs;
64 	DECLARE_BITMAP(hw_map, 64);
65 	DECLARE_BITMAP(sw_map, 64);
66 	DECLARE_BITMAP(state, 64);
67 	DECLARE_BITMAP(last_irq_read, 64);
68 	DECLARE_BITMAP(dir, 64);
69 	spinlock_t gpio_lock;	/* For serializing operations */
70 	int irq;
71 	DECLARE_BITMAP(enable, 64);
72 	DECLARE_BITMAP(rising_edge, 64);
73 	DECLARE_BITMAP(falling_edge, 64);
74 	struct clk *clk;
75 };
76 
xgpio_from_bit(struct xgpio_instance * chip,int bit)77 static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
78 {
79 	return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
80 }
81 
xgpio_to_bit(struct xgpio_instance * chip,int gpio)82 static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
83 {
84 	return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
85 }
86 
xgpio_get_value32(const unsigned long * map,int bit)87 static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
88 {
89 	const size_t index = BIT_WORD(bit);
90 	const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
91 
92 	return (map[index] >> offset) & 0xFFFFFFFFul;
93 }
94 
xgpio_set_value32(unsigned long * map,int bit,u32 v)95 static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
96 {
97 	const size_t index = BIT_WORD(bit);
98 	const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
99 
100 	map[index] &= ~(0xFFFFFFFFul << offset);
101 	map[index] |= (unsigned long)v << offset;
102 }
103 
xgpio_regoffset(struct xgpio_instance * chip,int ch)104 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
105 {
106 	switch (ch) {
107 	case 0:
108 		return XGPIO_CHANNEL0_OFFSET;
109 	case 1:
110 		return XGPIO_CHANNEL1_OFFSET;
111 	default:
112 		return -EINVAL;
113 	}
114 }
115 
xgpio_read_ch(struct xgpio_instance * chip,int reg,int bit,unsigned long * a)116 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
117 {
118 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
119 
120 	xgpio_set_value32(a, bit, xgpio_readreg(addr));
121 }
122 
xgpio_write_ch(struct xgpio_instance * chip,int reg,int bit,unsigned long * a)123 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
124 {
125 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
126 
127 	xgpio_writereg(addr, xgpio_get_value32(a, bit));
128 }
129 
xgpio_read_ch_all(struct xgpio_instance * chip,int reg,unsigned long * a)130 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
131 {
132 	int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
133 
134 	for (bit = 0; bit <= lastbit ; bit += 32)
135 		xgpio_read_ch(chip, reg, bit, a);
136 }
137 
xgpio_write_ch_all(struct xgpio_instance * chip,int reg,unsigned long * a)138 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
139 {
140 	int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
141 
142 	for (bit = 0; bit <= lastbit ; bit += 32)
143 		xgpio_write_ch(chip, reg, bit, a);
144 }
145 
146 /**
147  * xgpio_get - Read the specified signal of the GPIO device.
148  * @gc:     Pointer to gpio_chip device structure.
149  * @gpio:   GPIO signal number.
150  *
151  * This function reads the specified signal of the GPIO device.
152  *
153  * Return:
154  * 0 if direction of GPIO signals is set as input otherwise it
155  * returns negative error value.
156  */
xgpio_get(struct gpio_chip * gc,unsigned int gpio)157 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
158 {
159 	struct xgpio_instance *chip = gpiochip_get_data(gc);
160 	int bit = xgpio_to_bit(chip, gpio);
161 	DECLARE_BITMAP(state, 64);
162 
163 	xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
164 
165 	return test_bit(bit, state);
166 }
167 
168 /**
169  * xgpio_set - Write the specified signal of the GPIO device.
170  * @gc:     Pointer to gpio_chip device structure.
171  * @gpio:   GPIO signal number.
172  * @val:    Value to be written to specified signal.
173  *
174  * This function writes the specified value in to the specified signal of the
175  * GPIO device.
176  */
xgpio_set(struct gpio_chip * gc,unsigned int gpio,int val)177 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
178 {
179 	unsigned long flags;
180 	struct xgpio_instance *chip = gpiochip_get_data(gc);
181 	int bit = xgpio_to_bit(chip, gpio);
182 
183 	spin_lock_irqsave(&chip->gpio_lock, flags);
184 
185 	/* Write to GPIO signal and set its direction to output */
186 	__assign_bit(bit, chip->state, val);
187 
188 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
189 
190 	spin_unlock_irqrestore(&chip->gpio_lock, flags);
191 }
192 
193 /**
194  * xgpio_set_multiple - Write the specified signals of the GPIO device.
195  * @gc:     Pointer to gpio_chip device structure.
196  * @mask:   Mask of the GPIOS to modify.
197  * @bits:   Value to be wrote on each GPIO
198  *
199  * This function writes the specified values into the specified signals of the
200  * GPIO devices.
201  */
xgpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)202 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
203 			       unsigned long *bits)
204 {
205 	DECLARE_BITMAP(hw_mask, 64);
206 	DECLARE_BITMAP(hw_bits, 64);
207 	DECLARE_BITMAP(state, 64);
208 	unsigned long flags;
209 	struct xgpio_instance *chip = gpiochip_get_data(gc);
210 
211 	bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
212 	bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
213 
214 	spin_lock_irqsave(&chip->gpio_lock, flags);
215 
216 	bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
217 
218 	xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
219 
220 	bitmap_copy(chip->state, state, 64);
221 
222 	spin_unlock_irqrestore(&chip->gpio_lock, flags);
223 }
224 
225 /**
226  * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
227  * @gc:     Pointer to gpio_chip device structure.
228  * @gpio:   GPIO signal number.
229  *
230  * Return:
231  * 0 - if direction of GPIO signals is set as input
232  * otherwise it returns negative error value.
233  */
xgpio_dir_in(struct gpio_chip * gc,unsigned int gpio)234 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
235 {
236 	unsigned long flags;
237 	struct xgpio_instance *chip = gpiochip_get_data(gc);
238 	int bit = xgpio_to_bit(chip, gpio);
239 
240 	spin_lock_irqsave(&chip->gpio_lock, flags);
241 
242 	/* Set the GPIO bit in shadow register and set direction as input */
243 	__set_bit(bit, chip->dir);
244 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
245 
246 	spin_unlock_irqrestore(&chip->gpio_lock, flags);
247 
248 	return 0;
249 }
250 
251 /**
252  * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
253  * @gc:     Pointer to gpio_chip device structure.
254  * @gpio:   GPIO signal number.
255  * @val:    Value to be written to specified signal.
256  *
257  * This function sets the direction of specified GPIO signal as output.
258  *
259  * Return:
260  * If all GPIO signals of GPIO chip is configured as input then it returns
261  * error otherwise it returns 0.
262  */
xgpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)263 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
264 {
265 	unsigned long flags;
266 	struct xgpio_instance *chip = gpiochip_get_data(gc);
267 	int bit = xgpio_to_bit(chip, gpio);
268 
269 	spin_lock_irqsave(&chip->gpio_lock, flags);
270 
271 	/* Write state of GPIO signal */
272 	__assign_bit(bit, chip->state, val);
273 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
274 
275 	/* Clear the GPIO bit in shadow register and set direction as output */
276 	__clear_bit(bit, chip->dir);
277 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
278 
279 	spin_unlock_irqrestore(&chip->gpio_lock, flags);
280 
281 	return 0;
282 }
283 
284 /**
285  * xgpio_save_regs - Set initial values of GPIO pins
286  * @chip: Pointer to GPIO instance
287  */
xgpio_save_regs(struct xgpio_instance * chip)288 static void xgpio_save_regs(struct xgpio_instance *chip)
289 {
290 	xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
291 	xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
292 }
293 
xgpio_request(struct gpio_chip * chip,unsigned int offset)294 static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
295 {
296 	int ret;
297 
298 	ret = pm_runtime_get_sync(chip->parent);
299 	/*
300 	 * If the device is already active pm_runtime_get() will return 1 on
301 	 * success, but gpio_request still needs to return 0.
302 	 */
303 	return ret < 0 ? ret : 0;
304 }
305 
xgpio_free(struct gpio_chip * chip,unsigned int offset)306 static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
307 {
308 	pm_runtime_put(chip->parent);
309 }
310 
xgpio_suspend(struct device * dev)311 static int __maybe_unused xgpio_suspend(struct device *dev)
312 {
313 	struct xgpio_instance *gpio = dev_get_drvdata(dev);
314 	struct irq_data *data = irq_get_irq_data(gpio->irq);
315 
316 	if (!data) {
317 		dev_dbg(dev, "IRQ not connected\n");
318 		return pm_runtime_force_suspend(dev);
319 	}
320 
321 	if (!irqd_is_wakeup_set(data))
322 		return pm_runtime_force_suspend(dev);
323 
324 	return 0;
325 }
326 
327 /**
328  * xgpio_remove - Remove method for the GPIO device.
329  * @pdev: pointer to the platform device
330  *
331  * This function remove gpiochips and frees all the allocated resources.
332  *
333  * Return: 0 always
334  */
xgpio_remove(struct platform_device * pdev)335 static int xgpio_remove(struct platform_device *pdev)
336 {
337 	struct xgpio_instance *gpio = platform_get_drvdata(pdev);
338 
339 	pm_runtime_get_sync(&pdev->dev);
340 	pm_runtime_put_noidle(&pdev->dev);
341 	pm_runtime_disable(&pdev->dev);
342 	clk_disable_unprepare(gpio->clk);
343 
344 	return 0;
345 }
346 
347 /**
348  * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
349  * @irq_data: per IRQ and chip data passed down to chip functions
350  * This currently does nothing, but irq_ack is unconditionally called by
351  * handle_edge_irq and therefore must be defined.
352  */
xgpio_irq_ack(struct irq_data * irq_data)353 static void xgpio_irq_ack(struct irq_data *irq_data)
354 {
355 }
356 
xgpio_resume(struct device * dev)357 static int __maybe_unused xgpio_resume(struct device *dev)
358 {
359 	struct xgpio_instance *gpio = dev_get_drvdata(dev);
360 	struct irq_data *data = irq_get_irq_data(gpio->irq);
361 
362 	if (!data) {
363 		dev_dbg(dev, "IRQ not connected\n");
364 		return pm_runtime_force_resume(dev);
365 	}
366 
367 	if (!irqd_is_wakeup_set(data))
368 		return pm_runtime_force_resume(dev);
369 
370 	return 0;
371 }
372 
xgpio_runtime_suspend(struct device * dev)373 static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
374 {
375 	struct xgpio_instance *gpio = dev_get_drvdata(dev);
376 
377 	clk_disable(gpio->clk);
378 
379 	return 0;
380 }
381 
xgpio_runtime_resume(struct device * dev)382 static int __maybe_unused xgpio_runtime_resume(struct device *dev)
383 {
384 	struct xgpio_instance *gpio = dev_get_drvdata(dev);
385 
386 	return clk_enable(gpio->clk);
387 }
388 
389 static const struct dev_pm_ops xgpio_dev_pm_ops = {
390 	SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
391 	SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
392 			   xgpio_runtime_resume, NULL)
393 };
394 
395 /**
396  * xgpio_irq_mask - Write the specified signal of the GPIO device.
397  * @irq_data: per IRQ and chip data passed down to chip functions
398  */
xgpio_irq_mask(struct irq_data * irq_data)399 static void xgpio_irq_mask(struct irq_data *irq_data)
400 {
401 	unsigned long flags;
402 	struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
403 	int irq_offset = irqd_to_hwirq(irq_data);
404 	int bit = xgpio_to_bit(chip, irq_offset);
405 	u32 mask = BIT(bit / 32), temp;
406 
407 	spin_lock_irqsave(&chip->gpio_lock, flags);
408 
409 	__clear_bit(bit, chip->enable);
410 
411 	if (xgpio_get_value32(chip->enable, bit) == 0) {
412 		/* Disable per channel interrupt */
413 		temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
414 		temp &= ~mask;
415 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
416 	}
417 	spin_unlock_irqrestore(&chip->gpio_lock, flags);
418 
419 	gpiochip_disable_irq(&chip->gc, irq_offset);
420 }
421 
422 /**
423  * xgpio_irq_unmask - Write the specified signal of the GPIO device.
424  * @irq_data: per IRQ and chip data passed down to chip functions
425  */
xgpio_irq_unmask(struct irq_data * irq_data)426 static void xgpio_irq_unmask(struct irq_data *irq_data)
427 {
428 	unsigned long flags;
429 	struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
430 	int irq_offset = irqd_to_hwirq(irq_data);
431 	int bit = xgpio_to_bit(chip, irq_offset);
432 	u32 old_enable = xgpio_get_value32(chip->enable, bit);
433 	u32 mask = BIT(bit / 32), val;
434 
435 	gpiochip_enable_irq(&chip->gc, irq_offset);
436 
437 	spin_lock_irqsave(&chip->gpio_lock, flags);
438 
439 	__set_bit(bit, chip->enable);
440 
441 	if (old_enable == 0) {
442 		/* Clear any existing per-channel interrupts */
443 		val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
444 		val &= mask;
445 		xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
446 
447 		/* Update GPIO IRQ read data before enabling interrupt*/
448 		xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
449 
450 		/* Enable per channel interrupt */
451 		val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
452 		val |= mask;
453 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
454 	}
455 
456 	spin_unlock_irqrestore(&chip->gpio_lock, flags);
457 }
458 
459 /**
460  * xgpio_set_irq_type - Write the specified signal of the GPIO device.
461  * @irq_data: Per IRQ and chip data passed down to chip functions
462  * @type: Interrupt type that is to be set for the gpio pin
463  *
464  * Return:
465  * 0 if interrupt type is supported otherwise -EINVAL
466  */
xgpio_set_irq_type(struct irq_data * irq_data,unsigned int type)467 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
468 {
469 	struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
470 	int irq_offset = irqd_to_hwirq(irq_data);
471 	int bit = xgpio_to_bit(chip, irq_offset);
472 
473 	/*
474 	 * The Xilinx GPIO hardware provides a single interrupt status
475 	 * indication for any state change in a given GPIO channel (bank).
476 	 * Therefore, only rising edge or falling edge triggers are
477 	 * supported.
478 	 */
479 	switch (type & IRQ_TYPE_SENSE_MASK) {
480 	case IRQ_TYPE_EDGE_BOTH:
481 		__set_bit(bit, chip->rising_edge);
482 		__set_bit(bit, chip->falling_edge);
483 		break;
484 	case IRQ_TYPE_EDGE_RISING:
485 		__set_bit(bit, chip->rising_edge);
486 		__clear_bit(bit, chip->falling_edge);
487 		break;
488 	case IRQ_TYPE_EDGE_FALLING:
489 		__clear_bit(bit, chip->rising_edge);
490 		__set_bit(bit, chip->falling_edge);
491 		break;
492 	default:
493 		return -EINVAL;
494 	}
495 
496 	irq_set_handler_locked(irq_data, handle_edge_irq);
497 	return 0;
498 }
499 
500 /**
501  * xgpio_irqhandler - Gpio interrupt service routine
502  * @desc: Pointer to interrupt description
503  */
xgpio_irqhandler(struct irq_desc * desc)504 static void xgpio_irqhandler(struct irq_desc *desc)
505 {
506 	struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
507 	struct gpio_chip *gc = &chip->gc;
508 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
509 	DECLARE_BITMAP(rising, 64);
510 	DECLARE_BITMAP(falling, 64);
511 	DECLARE_BITMAP(all, 64);
512 	int irq_offset;
513 	u32 status;
514 	u32 bit;
515 
516 	status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
517 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
518 
519 	chained_irq_enter(irqchip, desc);
520 
521 	spin_lock(&chip->gpio_lock);
522 
523 	xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
524 
525 	bitmap_complement(rising, chip->last_irq_read, 64);
526 	bitmap_and(rising, rising, all, 64);
527 	bitmap_and(rising, rising, chip->enable, 64);
528 	bitmap_and(rising, rising, chip->rising_edge, 64);
529 
530 	bitmap_complement(falling, all, 64);
531 	bitmap_and(falling, falling, chip->last_irq_read, 64);
532 	bitmap_and(falling, falling, chip->enable, 64);
533 	bitmap_and(falling, falling, chip->falling_edge, 64);
534 
535 	bitmap_copy(chip->last_irq_read, all, 64);
536 	bitmap_or(all, rising, falling, 64);
537 
538 	spin_unlock(&chip->gpio_lock);
539 
540 	dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
541 
542 	for_each_set_bit(bit, all, 64) {
543 		irq_offset = xgpio_from_bit(chip, bit);
544 		generic_handle_domain_irq(gc->irq.domain, irq_offset);
545 	}
546 
547 	chained_irq_exit(irqchip, desc);
548 }
549 
550 static const struct irq_chip xgpio_irq_chip = {
551 	.name = "gpio-xilinx",
552 	.irq_ack = xgpio_irq_ack,
553 	.irq_mask = xgpio_irq_mask,
554 	.irq_unmask = xgpio_irq_unmask,
555 	.irq_set_type = xgpio_set_irq_type,
556 	.flags = IRQCHIP_IMMUTABLE,
557 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
558 };
559 
560 /**
561  * xgpio_probe - Probe method for the GPIO device.
562  * @pdev: pointer to the platform device
563  *
564  * Return:
565  * It returns 0, if the driver is bound to the GPIO device, or
566  * a negative value if there is an error.
567  */
xgpio_probe(struct platform_device * pdev)568 static int xgpio_probe(struct platform_device *pdev)
569 {
570 	struct xgpio_instance *chip;
571 	int status = 0;
572 	struct device_node *np = pdev->dev.of_node;
573 	u32 is_dual = 0;
574 	u32 width[2];
575 	u32 state[2];
576 	u32 dir[2];
577 	struct gpio_irq_chip *girq;
578 	u32 temp;
579 
580 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
581 	if (!chip)
582 		return -ENOMEM;
583 
584 	platform_set_drvdata(pdev, chip);
585 
586 	/* First, check if the device is dual-channel */
587 	of_property_read_u32(np, "xlnx,is-dual", &is_dual);
588 
589 	/* Setup defaults */
590 	memset32(width, 0, ARRAY_SIZE(width));
591 	memset32(state, 0, ARRAY_SIZE(state));
592 	memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
593 
594 	/* Update GPIO state shadow register with default value */
595 	of_property_read_u32(np, "xlnx,dout-default", &state[0]);
596 	of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
597 
598 	bitmap_from_arr32(chip->state, state, 64);
599 
600 	/* Update GPIO direction shadow register with default value */
601 	of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
602 	of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
603 
604 	bitmap_from_arr32(chip->dir, dir, 64);
605 
606 	/*
607 	 * Check device node and parent device node for device width
608 	 * and assume default width of 32
609 	 */
610 	if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
611 		width[0] = 32;
612 
613 	if (width[0] > 32)
614 		return -EINVAL;
615 
616 	if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
617 		width[1] = 32;
618 
619 	if (width[1] > 32)
620 		return -EINVAL;
621 
622 	/* Setup software pin mapping */
623 	bitmap_set(chip->sw_map, 0, width[0] + width[1]);
624 
625 	/* Setup hardware pin mapping */
626 	bitmap_set(chip->hw_map,  0, width[0]);
627 	bitmap_set(chip->hw_map, 32, width[1]);
628 
629 	spin_lock_init(&chip->gpio_lock);
630 
631 	chip->gc.base = -1;
632 	chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
633 	chip->gc.parent = &pdev->dev;
634 	chip->gc.direction_input = xgpio_dir_in;
635 	chip->gc.direction_output = xgpio_dir_out;
636 	chip->gc.get = xgpio_get;
637 	chip->gc.set = xgpio_set;
638 	chip->gc.request = xgpio_request;
639 	chip->gc.free = xgpio_free;
640 	chip->gc.set_multiple = xgpio_set_multiple;
641 
642 	chip->gc.label = dev_name(&pdev->dev);
643 
644 	chip->regs = devm_platform_ioremap_resource(pdev, 0);
645 	if (IS_ERR(chip->regs)) {
646 		dev_err(&pdev->dev, "failed to ioremap memory resource\n");
647 		return PTR_ERR(chip->regs);
648 	}
649 
650 	chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
651 	if (IS_ERR(chip->clk))
652 		return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
653 
654 	status = clk_prepare_enable(chip->clk);
655 	if (status < 0) {
656 		dev_err(&pdev->dev, "Failed to prepare clk\n");
657 		return status;
658 	}
659 	pm_runtime_get_noresume(&pdev->dev);
660 	pm_runtime_set_active(&pdev->dev);
661 	pm_runtime_enable(&pdev->dev);
662 
663 	xgpio_save_regs(chip);
664 
665 	chip->irq = platform_get_irq_optional(pdev, 0);
666 	if (chip->irq <= 0)
667 		goto skip_irq;
668 
669 	/* Disable per-channel interrupts */
670 	xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
671 	/* Clear any existing per-channel interrupts */
672 	temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
673 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
674 	/* Enable global interrupts */
675 	xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
676 
677 	girq = &chip->gc.irq;
678 	gpio_irq_chip_set_chip(girq, &xgpio_irq_chip);
679 	girq->parent_handler = xgpio_irqhandler;
680 	girq->num_parents = 1;
681 	girq->parents = devm_kcalloc(&pdev->dev, 1,
682 				     sizeof(*girq->parents),
683 				     GFP_KERNEL);
684 	if (!girq->parents) {
685 		status = -ENOMEM;
686 		goto err_pm_put;
687 	}
688 	girq->parents[0] = chip->irq;
689 	girq->default_type = IRQ_TYPE_NONE;
690 	girq->handler = handle_bad_irq;
691 
692 skip_irq:
693 	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
694 	if (status) {
695 		dev_err(&pdev->dev, "failed to add GPIO chip\n");
696 		goto err_pm_put;
697 	}
698 
699 	pm_runtime_put(&pdev->dev);
700 	return 0;
701 
702 err_pm_put:
703 	pm_runtime_disable(&pdev->dev);
704 	pm_runtime_put_noidle(&pdev->dev);
705 	clk_disable_unprepare(chip->clk);
706 	return status;
707 }
708 
709 static const struct of_device_id xgpio_of_match[] = {
710 	{ .compatible = "xlnx,xps-gpio-1.00.a", },
711 	{ /* end of list */ },
712 };
713 
714 MODULE_DEVICE_TABLE(of, xgpio_of_match);
715 
716 static struct platform_driver xgpio_plat_driver = {
717 	.probe		= xgpio_probe,
718 	.remove		= xgpio_remove,
719 	.driver		= {
720 			.name = "gpio-xilinx",
721 			.of_match_table	= xgpio_of_match,
722 			.pm = &xgpio_dev_pm_ops,
723 	},
724 };
725 
xgpio_init(void)726 static int __init xgpio_init(void)
727 {
728 	return platform_driver_register(&xgpio_plat_driver);
729 }
730 
731 subsys_initcall(xgpio_init);
732 
xgpio_exit(void)733 static void __exit xgpio_exit(void)
734 {
735 	platform_driver_unregister(&xgpio_plat_driver);
736 }
737 module_exit(xgpio_exit);
738 
739 MODULE_AUTHOR("Xilinx, Inc.");
740 MODULE_DESCRIPTION("Xilinx GPIO driver");
741 MODULE_LICENSE("GPL");
742