1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device.
3  *
4  * This is a new flat driver which is based on the original emac_lite
5  * driver from John Williams <john.williams@xilinx.com>.
6  *
7  * Copyright (c) 2007 - 2013 Xilinx, Inc.
8  */
9 
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/uaccess.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/skbuff.h>
16 #include <linux/ethtool.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_net.h>
23 #include <linux/phy.h>
24 #include <linux/interrupt.h>
25 #include <linux/iopoll.h>
26 
27 #define DRIVER_NAME "xilinx_emaclite"
28 
29 /* Register offsets for the EmacLite Core */
30 #define XEL_TXBUFF_OFFSET	0x0		/* Transmit Buffer */
31 #define XEL_MDIOADDR_OFFSET	0x07E4		/* MDIO Address Register */
32 #define XEL_MDIOWR_OFFSET	0x07E8		/* MDIO Write Data Register */
33 #define XEL_MDIORD_OFFSET	0x07EC		/* MDIO Read Data Register */
34 #define XEL_MDIOCTRL_OFFSET	0x07F0		/* MDIO Control Register */
35 #define XEL_GIER_OFFSET		0x07F8		/* GIE Register */
36 #define XEL_TSR_OFFSET		0x07FC		/* Tx status */
37 #define XEL_TPLR_OFFSET		0x07F4		/* Tx packet length */
38 
39 #define XEL_RXBUFF_OFFSET	0x1000		/* Receive Buffer */
40 #define XEL_RPLR_OFFSET		0x100C		/* Rx packet length */
41 #define XEL_RSR_OFFSET		0x17FC		/* Rx status */
42 
43 #define XEL_BUFFER_OFFSET	0x0800		/* Next Tx/Rx buffer's offset */
44 
45 /* MDIO Address Register Bit Masks */
46 #define XEL_MDIOADDR_REGADR_MASK  0x0000001F	/* Register Address */
47 #define XEL_MDIOADDR_PHYADR_MASK  0x000003E0	/* PHY Address */
48 #define XEL_MDIOADDR_PHYADR_SHIFT 5
49 #define XEL_MDIOADDR_OP_MASK	  0x00000400	/* RD/WR Operation */
50 
51 /* MDIO Write Data Register Bit Masks */
52 #define XEL_MDIOWR_WRDATA_MASK	  0x0000FFFF	/* Data to be Written */
53 
54 /* MDIO Read Data Register Bit Masks */
55 #define XEL_MDIORD_RDDATA_MASK	  0x0000FFFF	/* Data to be Read */
56 
57 /* MDIO Control Register Bit Masks */
58 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001	/* MDIO Status Mask */
59 #define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008	/* MDIO Enable */
60 
61 /* Global Interrupt Enable Register (GIER) Bit Masks */
62 #define XEL_GIER_GIE_MASK	0x80000000	/* Global Enable */
63 
64 /* Transmit Status Register (TSR) Bit Masks */
65 #define XEL_TSR_XMIT_BUSY_MASK	 0x00000001	/* Tx complete */
66 #define XEL_TSR_PROGRAM_MASK	 0x00000002	/* Program the MAC address */
67 #define XEL_TSR_XMIT_IE_MASK	 0x00000008	/* Tx interrupt enable bit */
68 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000	/* Buffer is active, SW bit
69 						 * only. This is not documented
70 						 * in the HW spec
71 						 */
72 
73 /* Define for programming the MAC address into the EmacLite */
74 #define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
75 
76 /* Receive Status Register (RSR) */
77 #define XEL_RSR_RECV_DONE_MASK	0x00000001	/* Rx complete */
78 #define XEL_RSR_RECV_IE_MASK	0x00000008	/* Rx interrupt enable bit */
79 
80 /* Transmit Packet Length Register (TPLR) */
81 #define XEL_TPLR_LENGTH_MASK	0x0000FFFF	/* Tx packet length */
82 
83 /* Receive Packet Length Register (RPLR) */
84 #define XEL_RPLR_LENGTH_MASK	0x0000FFFF	/* Rx packet length */
85 
86 #define XEL_HEADER_OFFSET	12		/* Offset to length field */
87 #define XEL_HEADER_SHIFT	16		/* Shift value for length */
88 
89 /* General Ethernet Definitions */
90 #define XEL_ARP_PACKET_SIZE		28	/* Max ARP packet size */
91 #define XEL_HEADER_IP_LENGTH_OFFSET	16	/* IP Length Offset */
92 
93 #define TX_TIMEOUT		(60 * HZ)	/* Tx timeout is 60 seconds. */
94 
95 #ifdef __BIG_ENDIAN
96 #define xemaclite_readl		ioread32be
97 #define xemaclite_writel	iowrite32be
98 #else
99 #define xemaclite_readl		ioread32
100 #define xemaclite_writel	iowrite32
101 #endif
102 
103 /**
104  * struct net_local - Our private per device data
105  * @ndev:		instance of the network device
106  * @tx_ping_pong:	indicates whether Tx Pong buffer is configured in HW
107  * @rx_ping_pong:	indicates whether Rx Pong buffer is configured in HW
108  * @next_tx_buf_to_use:	next Tx buffer to write to
109  * @next_rx_buf_to_use:	next Rx buffer to read from
110  * @base_addr:		base address of the Emaclite device
111  * @reset_lock:		lock to serialize xmit and tx_timeout execution
112  * @deferred_skb:	holds an skb (for transmission at a later time) when the
113  *			Tx buffer is not free
114  * @phy_dev:		pointer to the PHY device
115  * @phy_node:		pointer to the PHY device node
116  * @mii_bus:		pointer to the MII bus
117  * @last_link:		last link status
118  */
119 struct net_local {
120 	struct net_device *ndev;
121 
122 	bool tx_ping_pong;
123 	bool rx_ping_pong;
124 	u32 next_tx_buf_to_use;
125 	u32 next_rx_buf_to_use;
126 	void __iomem *base_addr;
127 
128 	spinlock_t reset_lock; /* serialize xmit and tx_timeout execution */
129 	struct sk_buff *deferred_skb;
130 
131 	struct phy_device *phy_dev;
132 	struct device_node *phy_node;
133 
134 	struct mii_bus *mii_bus;
135 
136 	int last_link;
137 };
138 
139 /*************************/
140 /* EmacLite driver calls */
141 /*************************/
142 
143 /**
144  * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device
145  * @drvdata:	Pointer to the Emaclite device private data
146  *
147  * This function enables the Tx and Rx interrupts for the Emaclite device along
148  * with the Global Interrupt Enable.
149  */
xemaclite_enable_interrupts(struct net_local * drvdata)150 static void xemaclite_enable_interrupts(struct net_local *drvdata)
151 {
152 	u32 reg_data;
153 
154 	/* Enable the Tx interrupts for the first Buffer */
155 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
156 	xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
157 			 drvdata->base_addr + XEL_TSR_OFFSET);
158 
159 	/* Enable the Rx interrupts for the first buffer */
160 	xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
161 
162 	/* Enable the Global Interrupt Enable */
163 	xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
164 }
165 
166 /**
167  * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device
168  * @drvdata:	Pointer to the Emaclite device private data
169  *
170  * This function disables the Tx and Rx interrupts for the Emaclite device,
171  * along with the Global Interrupt Enable.
172  */
xemaclite_disable_interrupts(struct net_local * drvdata)173 static void xemaclite_disable_interrupts(struct net_local *drvdata)
174 {
175 	u32 reg_data;
176 
177 	/* Disable the Global Interrupt Enable */
178 	xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
179 
180 	/* Disable the Tx interrupts for the first buffer */
181 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
182 	xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
183 			 drvdata->base_addr + XEL_TSR_OFFSET);
184 
185 	/* Disable the Rx interrupts for the first buffer */
186 	reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);
187 	xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
188 			 drvdata->base_addr + XEL_RSR_OFFSET);
189 }
190 
191 /**
192  * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address
193  * @src_ptr:	Void pointer to the 16-bit aligned source address
194  * @dest_ptr:	Pointer to the 32-bit aligned destination address
195  * @length:	Number bytes to write from source to destination
196  *
197  * This function writes data from a 16-bit aligned buffer to a 32-bit aligned
198  * address in the EmacLite device.
199  */
xemaclite_aligned_write(const void * src_ptr,u32 * dest_ptr,unsigned int length)200 static void xemaclite_aligned_write(const void *src_ptr, u32 *dest_ptr,
201 				    unsigned int length)
202 {
203 	const u16 *from_u16_ptr;
204 	u32 align_buffer;
205 	u32 *to_u32_ptr;
206 	u16 *to_u16_ptr;
207 
208 	to_u32_ptr = dest_ptr;
209 	from_u16_ptr = src_ptr;
210 	align_buffer = 0;
211 
212 	for (; length > 3; length -= 4) {
213 		to_u16_ptr = (u16 *)&align_buffer;
214 		*to_u16_ptr++ = *from_u16_ptr++;
215 		*to_u16_ptr++ = *from_u16_ptr++;
216 
217 		/* This barrier resolves occasional issues seen around
218 		 * cases where the data is not properly flushed out
219 		 * from the processor store buffers to the destination
220 		 * memory locations.
221 		 */
222 		wmb();
223 
224 		/* Output a word */
225 		*to_u32_ptr++ = align_buffer;
226 	}
227 	if (length) {
228 		u8 *from_u8_ptr, *to_u8_ptr;
229 
230 		/* Set up to output the remaining data */
231 		align_buffer = 0;
232 		to_u8_ptr = (u8 *)&align_buffer;
233 		from_u8_ptr = (u8 *)from_u16_ptr;
234 
235 		/* Output the remaining data */
236 		for (; length > 0; length--)
237 			*to_u8_ptr++ = *from_u8_ptr++;
238 
239 		/* This barrier resolves occasional issues seen around
240 		 * cases where the data is not properly flushed out
241 		 * from the processor store buffers to the destination
242 		 * memory locations.
243 		 */
244 		wmb();
245 		*to_u32_ptr = align_buffer;
246 	}
247 }
248 
249 /**
250  * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer
251  * @src_ptr:	Pointer to the 32-bit aligned source address
252  * @dest_ptr:	Pointer to the 16-bit aligned destination address
253  * @length:	Number bytes to read from source to destination
254  *
255  * This function reads data from a 32-bit aligned address in the EmacLite device
256  * to a 16-bit aligned buffer.
257  */
xemaclite_aligned_read(u32 * src_ptr,u8 * dest_ptr,unsigned int length)258 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
259 				   unsigned int length)
260 {
261 	u16 *to_u16_ptr, *from_u16_ptr;
262 	u32 *from_u32_ptr;
263 	u32 align_buffer;
264 
265 	from_u32_ptr = src_ptr;
266 	to_u16_ptr = (u16 *)dest_ptr;
267 
268 	for (; length > 3; length -= 4) {
269 		/* Copy each word into the temporary buffer */
270 		align_buffer = *from_u32_ptr++;
271 		from_u16_ptr = (u16 *)&align_buffer;
272 
273 		/* Read data from source */
274 		*to_u16_ptr++ = *from_u16_ptr++;
275 		*to_u16_ptr++ = *from_u16_ptr++;
276 	}
277 
278 	if (length) {
279 		u8 *to_u8_ptr, *from_u8_ptr;
280 
281 		/* Set up to read the remaining data */
282 		to_u8_ptr = (u8 *)to_u16_ptr;
283 		align_buffer = *from_u32_ptr++;
284 		from_u8_ptr = (u8 *)&align_buffer;
285 
286 		/* Read the remaining data */
287 		for (; length > 0; length--)
288 			*to_u8_ptr = *from_u8_ptr;
289 	}
290 }
291 
292 /**
293  * xemaclite_send_data - Send an Ethernet frame
294  * @drvdata:	Pointer to the Emaclite device private data
295  * @data:	Pointer to the data to be sent
296  * @byte_count:	Total frame size, including header
297  *
298  * This function checks if the Tx buffer of the Emaclite device is free to send
299  * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it
300  * returns an error.
301  *
302  * Return:	0 upon success or -1 if the buffer(s) are full.
303  *
304  * Note:	The maximum Tx packet size can not be more than Ethernet header
305  *		(14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS.
306  */
xemaclite_send_data(struct net_local * drvdata,u8 * data,unsigned int byte_count)307 static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
308 			       unsigned int byte_count)
309 {
310 	u32 reg_data;
311 	void __iomem *addr;
312 
313 	/* Determine the expected Tx buffer address */
314 	addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
315 
316 	/* If the length is too large, truncate it */
317 	if (byte_count > ETH_FRAME_LEN)
318 		byte_count = ETH_FRAME_LEN;
319 
320 	/* Check if the expected buffer is available */
321 	reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
322 	if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
323 	     XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
324 		/* Switch to next buffer if configured */
325 		if (drvdata->tx_ping_pong != 0)
326 			drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
327 	} else if (drvdata->tx_ping_pong != 0) {
328 		/* If the expected buffer is full, try the other buffer,
329 		 * if it is configured in HW
330 		 */
331 
332 		addr = (void __iomem __force *)((uintptr_t __force)addr ^
333 						 XEL_BUFFER_OFFSET);
334 		reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
335 
336 		if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
337 		     XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
338 			return -1; /* Buffers were full, return failure */
339 	} else {
340 		return -1; /* Buffer was full, return failure */
341 	}
342 
343 	/* Write the frame to the buffer */
344 	xemaclite_aligned_write(data, (u32 __force *)addr, byte_count);
345 
346 	xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK),
347 			 addr + XEL_TPLR_OFFSET);
348 
349 	/* Update the Tx Status Register to indicate that there is a
350 	 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
351 	 * is used by the interrupt handler to check whether a frame
352 	 * has been transmitted
353 	 */
354 	reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
355 	reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
356 	xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET);
357 
358 	return 0;
359 }
360 
361 /**
362  * xemaclite_recv_data - Receive a frame
363  * @drvdata:	Pointer to the Emaclite device private data
364  * @data:	Address where the data is to be received
365  * @maxlen:    Maximum supported ethernet packet length
366  *
367  * This function is intended to be called from the interrupt context or
368  * with a wrapper which waits for the receive frame to be available.
369  *
370  * Return:	Total number of bytes received
371  */
xemaclite_recv_data(struct net_local * drvdata,u8 * data,int maxlen)372 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen)
373 {
374 	void __iomem *addr;
375 	u16 length, proto_type;
376 	u32 reg_data;
377 
378 	/* Determine the expected buffer address */
379 	addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
380 
381 	/* Verify which buffer has valid data */
382 	reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
383 
384 	if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
385 		if (drvdata->rx_ping_pong != 0)
386 			drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
387 	} else {
388 		/* The instance is out of sync, try other buffer if other
389 		 * buffer is configured, return 0 otherwise. If the instance is
390 		 * out of sync, do not update the 'next_rx_buf_to_use' since it
391 		 * will correct on subsequent calls
392 		 */
393 		if (drvdata->rx_ping_pong != 0)
394 			addr = (void __iomem __force *)
395 				((uintptr_t __force)addr ^
396 				 XEL_BUFFER_OFFSET);
397 		else
398 			return 0;	/* No data was available */
399 
400 		/* Verify that buffer has valid data */
401 		reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
402 		if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
403 		     XEL_RSR_RECV_DONE_MASK)
404 			return 0;	/* No data was available */
405 	}
406 
407 	/* Get the protocol type of the ethernet frame that arrived
408 	 */
409 	proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET +
410 			XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
411 			XEL_RPLR_LENGTH_MASK);
412 
413 	/* Check if received ethernet frame is a raw ethernet frame
414 	 * or an IP packet or an ARP packet
415 	 */
416 	if (proto_type > ETH_DATA_LEN) {
417 		if (proto_type == ETH_P_IP) {
418 			length = ((ntohl(xemaclite_readl(addr +
419 					XEL_HEADER_IP_LENGTH_OFFSET +
420 					XEL_RXBUFF_OFFSET)) >>
421 					XEL_HEADER_SHIFT) &
422 					XEL_RPLR_LENGTH_MASK);
423 			length = min_t(u16, length, ETH_DATA_LEN);
424 			length += ETH_HLEN + ETH_FCS_LEN;
425 
426 		} else if (proto_type == ETH_P_ARP) {
427 			length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
428 		} else {
429 			/* Field contains type other than IP or ARP, use max
430 			 * frame size and let user parse it
431 			 */
432 			length = ETH_FRAME_LEN + ETH_FCS_LEN;
433 		}
434 	} else {
435 		/* Use the length in the frame, plus the header and trailer */
436 		length = proto_type + ETH_HLEN + ETH_FCS_LEN;
437 	}
438 
439 	if (WARN_ON(length > maxlen))
440 		length = maxlen;
441 
442 	/* Read from the EmacLite device */
443 	xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET),
444 			       data, length);
445 
446 	/* Acknowledge the frame */
447 	reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
448 	reg_data &= ~XEL_RSR_RECV_DONE_MASK;
449 	xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET);
450 
451 	return length;
452 }
453 
454 /**
455  * xemaclite_update_address - Update the MAC address in the device
456  * @drvdata:	Pointer to the Emaclite device private data
457  * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value)
458  *
459  * Tx must be idle and Rx should be idle for deterministic results.
460  * It is recommended that this function should be called after the
461  * initialization and before transmission of any packets from the device.
462  * The MAC address can be programmed using any of the two transmit
463  * buffers (if configured).
464  */
xemaclite_update_address(struct net_local * drvdata,const u8 * address_ptr)465 static void xemaclite_update_address(struct net_local *drvdata,
466 				     const u8 *address_ptr)
467 {
468 	void __iomem *addr;
469 	u32 reg_data;
470 
471 	/* Determine the expected Tx buffer address */
472 	addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
473 
474 	xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN);
475 
476 	xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
477 
478 	/* Update the MAC address in the EmacLite */
479 	reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
480 	xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
481 
482 	/* Wait for EmacLite to finish with the MAC address update */
483 	while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &
484 		XEL_TSR_PROG_MAC_ADDR) != 0)
485 		;
486 }
487 
488 /**
489  * xemaclite_set_mac_address - Set the MAC address for this device
490  * @dev:	Pointer to the network device instance
491  * @address:	Void pointer to the sockaddr structure
492  *
493  * This function copies the HW address from the sockaddr structure to the
494  * net_device structure and updates the address in HW.
495  *
496  * Return:	Error if the net device is busy or 0 if the addr is set
497  *		successfully
498  */
xemaclite_set_mac_address(struct net_device * dev,void * address)499 static int xemaclite_set_mac_address(struct net_device *dev, void *address)
500 {
501 	struct net_local *lp = netdev_priv(dev);
502 	struct sockaddr *addr = address;
503 
504 	if (netif_running(dev))
505 		return -EBUSY;
506 
507 	eth_hw_addr_set(dev, addr->sa_data);
508 	xemaclite_update_address(lp, dev->dev_addr);
509 	return 0;
510 }
511 
512 /**
513  * xemaclite_tx_timeout - Callback for Tx Timeout
514  * @dev:	Pointer to the network device
515  * @txqueue:	Unused
516  *
517  * This function is called when Tx time out occurs for Emaclite device.
518  */
xemaclite_tx_timeout(struct net_device * dev,unsigned int txqueue)519 static void xemaclite_tx_timeout(struct net_device *dev, unsigned int txqueue)
520 {
521 	struct net_local *lp = netdev_priv(dev);
522 	unsigned long flags;
523 
524 	dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
525 		TX_TIMEOUT * 1000UL / HZ);
526 
527 	dev->stats.tx_errors++;
528 
529 	/* Reset the device */
530 	spin_lock_irqsave(&lp->reset_lock, flags);
531 
532 	/* Shouldn't really be necessary, but shouldn't hurt */
533 	netif_stop_queue(dev);
534 
535 	xemaclite_disable_interrupts(lp);
536 	xemaclite_enable_interrupts(lp);
537 
538 	if (lp->deferred_skb) {
539 		dev_kfree_skb_irq(lp->deferred_skb);
540 		lp->deferred_skb = NULL;
541 		dev->stats.tx_errors++;
542 	}
543 
544 	/* To exclude tx timeout */
545 	netif_trans_update(dev); /* prevent tx timeout */
546 
547 	/* We're all ready to go. Start the queue */
548 	netif_wake_queue(dev);
549 	spin_unlock_irqrestore(&lp->reset_lock, flags);
550 }
551 
552 /**********************/
553 /* Interrupt Handlers */
554 /**********************/
555 
556 /**
557  * xemaclite_tx_handler - Interrupt handler for frames sent
558  * @dev:	Pointer to the network device
559  *
560  * This function updates the number of packets transmitted and handles the
561  * deferred skb, if there is one.
562  */
xemaclite_tx_handler(struct net_device * dev)563 static void xemaclite_tx_handler(struct net_device *dev)
564 {
565 	struct net_local *lp = netdev_priv(dev);
566 
567 	dev->stats.tx_packets++;
568 
569 	if (!lp->deferred_skb)
570 		return;
571 
572 	if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data,
573 				lp->deferred_skb->len))
574 		return;
575 
576 	dev->stats.tx_bytes += lp->deferred_skb->len;
577 	dev_consume_skb_irq(lp->deferred_skb);
578 	lp->deferred_skb = NULL;
579 	netif_trans_update(dev); /* prevent tx timeout */
580 	netif_wake_queue(dev);
581 }
582 
583 /**
584  * xemaclite_rx_handler- Interrupt handler for frames received
585  * @dev:	Pointer to the network device
586  *
587  * This function allocates memory for a socket buffer, fills it with data
588  * received and hands it over to the TCP/IP stack.
589  */
xemaclite_rx_handler(struct net_device * dev)590 static void xemaclite_rx_handler(struct net_device *dev)
591 {
592 	struct net_local *lp = netdev_priv(dev);
593 	struct sk_buff *skb;
594 	u32 len;
595 
596 	len = ETH_FRAME_LEN + ETH_FCS_LEN;
597 	skb = netdev_alloc_skb(dev, len + NET_IP_ALIGN);
598 	if (!skb) {
599 		/* Couldn't get memory. */
600 		dev->stats.rx_dropped++;
601 		dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
602 		return;
603 	}
604 
605 	skb_reserve(skb, NET_IP_ALIGN);
606 
607 	len = xemaclite_recv_data(lp, (u8 *)skb->data, len);
608 
609 	if (!len) {
610 		dev->stats.rx_errors++;
611 		dev_kfree_skb_irq(skb);
612 		return;
613 	}
614 
615 	skb_put(skb, len);	/* Tell the skb how much data we got */
616 
617 	skb->protocol = eth_type_trans(skb, dev);
618 	skb_checksum_none_assert(skb);
619 
620 	dev->stats.rx_packets++;
621 	dev->stats.rx_bytes += len;
622 
623 	if (!skb_defer_rx_timestamp(skb))
624 		netif_rx(skb);	/* Send the packet upstream */
625 }
626 
627 /**
628  * xemaclite_interrupt - Interrupt handler for this driver
629  * @irq:	Irq of the Emaclite device
630  * @dev_id:	Void pointer to the network device instance used as callback
631  *		reference
632  *
633  * Return:	IRQ_HANDLED
634  *
635  * This function handles the Tx and Rx interrupts of the EmacLite device.
636  */
xemaclite_interrupt(int irq,void * dev_id)637 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
638 {
639 	bool tx_complete = false;
640 	struct net_device *dev = dev_id;
641 	struct net_local *lp = netdev_priv(dev);
642 	void __iomem *base_addr = lp->base_addr;
643 	u32 tx_status;
644 
645 	/* Check if there is Rx Data available */
646 	if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &
647 			 XEL_RSR_RECV_DONE_MASK) ||
648 	    (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
649 			 & XEL_RSR_RECV_DONE_MASK))
650 
651 		xemaclite_rx_handler(dev);
652 
653 	/* Check if the Transmission for the first buffer is completed */
654 	tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);
655 	if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
656 	    (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
657 		tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
658 		xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);
659 
660 		tx_complete = true;
661 	}
662 
663 	/* Check if the Transmission for the second buffer is completed */
664 	tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
665 	if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
666 	    (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
667 		tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
668 		xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
669 				 XEL_TSR_OFFSET);
670 
671 		tx_complete = true;
672 	}
673 
674 	/* If there was a Tx interrupt, call the Tx Handler */
675 	if (tx_complete != 0)
676 		xemaclite_tx_handler(dev);
677 
678 	return IRQ_HANDLED;
679 }
680 
681 /**********************/
682 /* MDIO Bus functions */
683 /**********************/
684 
685 /**
686  * xemaclite_mdio_wait - Wait for the MDIO to be ready to use
687  * @lp:		Pointer to the Emaclite device private data
688  *
689  * This function waits till the device is ready to accept a new MDIO
690  * request.
691  *
692  * Return:	0 for success or ETIMEDOUT for a timeout
693  */
694 
xemaclite_mdio_wait(struct net_local * lp)695 static int xemaclite_mdio_wait(struct net_local *lp)
696 {
697 	u32 val;
698 
699 	/* wait for the MDIO interface to not be busy or timeout
700 	 * after some time.
701 	 */
702 	return readx_poll_timeout(xemaclite_readl,
703 				  lp->base_addr + XEL_MDIOCTRL_OFFSET,
704 				  val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK),
705 				  1000, 20000);
706 }
707 
708 /**
709  * xemaclite_mdio_read - Read from a given MII management register
710  * @bus:	the mii_bus struct
711  * @phy_id:	the phy address
712  * @reg:	register number to read from
713  *
714  * This function waits till the device is ready to accept a new MDIO
715  * request and then writes the phy address to the MDIO Address register
716  * and reads data from MDIO Read Data register, when its available.
717  *
718  * Return:	Value read from the MII management register
719  */
xemaclite_mdio_read(struct mii_bus * bus,int phy_id,int reg)720 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
721 {
722 	struct net_local *lp = bus->priv;
723 	u32 ctrl_reg;
724 	u32 rc;
725 
726 	if (xemaclite_mdio_wait(lp))
727 		return -ETIMEDOUT;
728 
729 	/* Write the PHY address, register number and set the OP bit in the
730 	 * MDIO Address register. Set the Status bit in the MDIO Control
731 	 * register to start a MDIO read transaction.
732 	 */
733 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
734 	xemaclite_writel(XEL_MDIOADDR_OP_MASK |
735 			 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
736 			 lp->base_addr + XEL_MDIOADDR_OFFSET);
737 	xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
738 			 lp->base_addr + XEL_MDIOCTRL_OFFSET);
739 
740 	if (xemaclite_mdio_wait(lp))
741 		return -ETIMEDOUT;
742 
743 	rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);
744 
745 	dev_dbg(&lp->ndev->dev,
746 		"%s(phy_id=%i, reg=%x) == %x\n", __func__,
747 		phy_id, reg, rc);
748 
749 	return rc;
750 }
751 
752 /**
753  * xemaclite_mdio_write - Write to a given MII management register
754  * @bus:	the mii_bus struct
755  * @phy_id:	the phy address
756  * @reg:	register number to write to
757  * @val:	value to write to the register number specified by reg
758  *
759  * This function waits till the device is ready to accept a new MDIO
760  * request and then writes the val to the MDIO Write Data register.
761  *
762  * Return:      0 upon success or a negative error upon failure
763  */
xemaclite_mdio_write(struct mii_bus * bus,int phy_id,int reg,u16 val)764 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
765 				u16 val)
766 {
767 	struct net_local *lp = bus->priv;
768 	u32 ctrl_reg;
769 
770 	dev_dbg(&lp->ndev->dev,
771 		"%s(phy_id=%i, reg=%x, val=%x)\n", __func__,
772 		phy_id, reg, val);
773 
774 	if (xemaclite_mdio_wait(lp))
775 		return -ETIMEDOUT;
776 
777 	/* Write the PHY address, register number and clear the OP bit in the
778 	 * MDIO Address register and then write the value into the MDIO Write
779 	 * Data register. Finally, set the Status bit in the MDIO Control
780 	 * register to start a MDIO write transaction.
781 	 */
782 	ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
783 	xemaclite_writel(~XEL_MDIOADDR_OP_MASK &
784 			 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
785 			 lp->base_addr + XEL_MDIOADDR_OFFSET);
786 	xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
787 	xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
788 			 lp->base_addr + XEL_MDIOCTRL_OFFSET);
789 
790 	return 0;
791 }
792 
793 /**
794  * xemaclite_mdio_setup - Register mii_bus for the Emaclite device
795  * @lp:		Pointer to the Emaclite device private data
796  * @dev:	Pointer to OF device structure
797  *
798  * This function enables MDIO bus in the Emaclite device and registers a
799  * mii_bus.
800  *
801  * Return:	0 upon success or a negative error upon failure
802  */
xemaclite_mdio_setup(struct net_local * lp,struct device * dev)803 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
804 {
805 	struct mii_bus *bus;
806 	struct resource res;
807 	struct device_node *np = of_get_parent(lp->phy_node);
808 	struct device_node *npp;
809 	int rc, ret;
810 
811 	/* Don't register the MDIO bus if the phy_node or its parent node
812 	 * can't be found.
813 	 */
814 	if (!np) {
815 		dev_err(dev, "Failed to register mdio bus.\n");
816 		return -ENODEV;
817 	}
818 	npp = of_get_parent(np);
819 	ret = of_address_to_resource(npp, 0, &res);
820 	of_node_put(npp);
821 	if (ret) {
822 		dev_err(dev, "%s resource error!\n",
823 			dev->of_node->full_name);
824 		of_node_put(np);
825 		return ret;
826 	}
827 	if (lp->ndev->mem_start != res.start) {
828 		struct phy_device *phydev;
829 
830 		phydev = of_phy_find_device(lp->phy_node);
831 		if (!phydev)
832 			dev_info(dev,
833 				 "MDIO of the phy is not registered yet\n");
834 		else
835 			put_device(&phydev->mdio.dev);
836 		of_node_put(np);
837 		return 0;
838 	}
839 
840 	/* Enable the MDIO bus by asserting the enable bit in MDIO Control
841 	 * register.
842 	 */
843 	xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK,
844 			 lp->base_addr + XEL_MDIOCTRL_OFFSET);
845 
846 	bus = mdiobus_alloc();
847 	if (!bus) {
848 		dev_err(dev, "Failed to allocate mdiobus\n");
849 		of_node_put(np);
850 		return -ENOMEM;
851 	}
852 
853 	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
854 		 (unsigned long long)res.start);
855 	bus->priv = lp;
856 	bus->name = "Xilinx Emaclite MDIO";
857 	bus->read = xemaclite_mdio_read;
858 	bus->write = xemaclite_mdio_write;
859 	bus->parent = dev;
860 
861 	rc = of_mdiobus_register(bus, np);
862 	of_node_put(np);
863 	if (rc) {
864 		dev_err(dev, "Failed to register mdio bus.\n");
865 		goto err_register;
866 	}
867 
868 	lp->mii_bus = bus;
869 
870 	return 0;
871 
872 err_register:
873 	mdiobus_free(bus);
874 	return rc;
875 }
876 
877 /**
878  * xemaclite_adjust_link - Link state callback for the Emaclite device
879  * @ndev: pointer to net_device struct
880  *
881  * There's nothing in the Emaclite device to be configured when the link
882  * state changes. We just print the status.
883  */
xemaclite_adjust_link(struct net_device * ndev)884 static void xemaclite_adjust_link(struct net_device *ndev)
885 {
886 	struct net_local *lp = netdev_priv(ndev);
887 	struct phy_device *phy = lp->phy_dev;
888 	int link_state;
889 
890 	/* hash together the state values to decide if something has changed */
891 	link_state = phy->speed | (phy->duplex << 1) | phy->link;
892 
893 	if (lp->last_link != link_state) {
894 		lp->last_link = link_state;
895 		phy_print_status(phy);
896 	}
897 }
898 
899 /**
900  * xemaclite_open - Open the network device
901  * @dev:	Pointer to the network device
902  *
903  * This function sets the MAC address, requests an IRQ and enables interrupts
904  * for the Emaclite device and starts the Tx queue.
905  * It also connects to the phy device, if MDIO is included in Emaclite device.
906  *
907  * Return:	0 on success. -ENODEV, if PHY cannot be connected.
908  *		Non-zero error value on failure.
909  */
xemaclite_open(struct net_device * dev)910 static int xemaclite_open(struct net_device *dev)
911 {
912 	struct net_local *lp = netdev_priv(dev);
913 	int retval;
914 
915 	/* Just to be safe, stop the device first */
916 	xemaclite_disable_interrupts(lp);
917 
918 	if (lp->phy_node) {
919 		lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
920 					     xemaclite_adjust_link, 0,
921 					     PHY_INTERFACE_MODE_MII);
922 		if (!lp->phy_dev) {
923 			dev_err(&lp->ndev->dev, "of_phy_connect() failed\n");
924 			return -ENODEV;
925 		}
926 
927 		/* EmacLite doesn't support giga-bit speeds */
928 		phy_set_max_speed(lp->phy_dev, SPEED_100);
929 		phy_start(lp->phy_dev);
930 	}
931 
932 	/* Set the MAC address each time opened */
933 	xemaclite_update_address(lp, dev->dev_addr);
934 
935 	/* Grab the IRQ */
936 	retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev);
937 	if (retval) {
938 		dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
939 			dev->irq);
940 		if (lp->phy_dev)
941 			phy_disconnect(lp->phy_dev);
942 		lp->phy_dev = NULL;
943 
944 		return retval;
945 	}
946 
947 	/* Enable Interrupts */
948 	xemaclite_enable_interrupts(lp);
949 
950 	/* We're ready to go */
951 	netif_start_queue(dev);
952 
953 	return 0;
954 }
955 
956 /**
957  * xemaclite_close - Close the network device
958  * @dev:	Pointer to the network device
959  *
960  * This function stops the Tx queue, disables interrupts and frees the IRQ for
961  * the Emaclite device.
962  * It also disconnects the phy device associated with the Emaclite device.
963  *
964  * Return:	0, always.
965  */
xemaclite_close(struct net_device * dev)966 static int xemaclite_close(struct net_device *dev)
967 {
968 	struct net_local *lp = netdev_priv(dev);
969 
970 	netif_stop_queue(dev);
971 	xemaclite_disable_interrupts(lp);
972 	free_irq(dev->irq, dev);
973 
974 	if (lp->phy_dev)
975 		phy_disconnect(lp->phy_dev);
976 	lp->phy_dev = NULL;
977 
978 	return 0;
979 }
980 
981 /**
982  * xemaclite_send - Transmit a frame
983  * @orig_skb:	Pointer to the socket buffer to be transmitted
984  * @dev:	Pointer to the network device
985  *
986  * This function checks if the Tx buffer of the Emaclite device is free to send
987  * data. If so, it fills the Tx buffer with data from socket buffer data,
988  * updates the stats and frees the socket buffer. The Tx completion is signaled
989  * by an interrupt. If the Tx buffer isn't free, then the socket buffer is
990  * deferred and the Tx queue is stopped so that the deferred socket buffer can
991  * be transmitted when the Emaclite device is free to transmit data.
992  *
993  * Return:	NETDEV_TX_OK, always.
994  */
995 static netdev_tx_t
xemaclite_send(struct sk_buff * orig_skb,struct net_device * dev)996 xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
997 {
998 	struct net_local *lp = netdev_priv(dev);
999 	struct sk_buff *new_skb;
1000 	unsigned int len;
1001 	unsigned long flags;
1002 
1003 	len = orig_skb->len;
1004 
1005 	new_skb = orig_skb;
1006 
1007 	spin_lock_irqsave(&lp->reset_lock, flags);
1008 	if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) {
1009 		/* If the Emaclite Tx buffer is busy, stop the Tx queue and
1010 		 * defer the skb for transmission during the ISR, after the
1011 		 * current transmission is complete
1012 		 */
1013 		netif_stop_queue(dev);
1014 		lp->deferred_skb = new_skb;
1015 		/* Take the time stamp now, since we can't do this in an ISR. */
1016 		skb_tx_timestamp(new_skb);
1017 		spin_unlock_irqrestore(&lp->reset_lock, flags);
1018 		return NETDEV_TX_OK;
1019 	}
1020 	spin_unlock_irqrestore(&lp->reset_lock, flags);
1021 
1022 	skb_tx_timestamp(new_skb);
1023 
1024 	dev->stats.tx_bytes += len;
1025 	dev_consume_skb_any(new_skb);
1026 
1027 	return NETDEV_TX_OK;
1028 }
1029 
1030 /**
1031  * get_bool - Get a parameter from the OF device
1032  * @ofdev:	Pointer to OF device structure
1033  * @s:		Property to be retrieved
1034  *
1035  * This function looks for a property in the device node and returns the value
1036  * of the property if its found or 0 if the property is not found.
1037  *
1038  * Return:	Value of the parameter if the parameter is found, or 0 otherwise
1039  */
get_bool(struct platform_device * ofdev,const char * s)1040 static bool get_bool(struct platform_device *ofdev, const char *s)
1041 {
1042 	u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL);
1043 
1044 	if (!p) {
1045 		dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s);
1046 		return false;
1047 	}
1048 
1049 	return (bool)*p;
1050 }
1051 
1052 /**
1053  * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info
1054  * @ndev:       Pointer to net_device structure
1055  * @ed:         Pointer to ethtool_drvinfo structure
1056  *
1057  * This implements ethtool command for getting the driver information.
1058  * Issue "ethtool -i ethX" under linux prompt to execute this function.
1059  */
xemaclite_ethtools_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * ed)1060 static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev,
1061 					   struct ethtool_drvinfo *ed)
1062 {
1063 	strscpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1064 }
1065 
1066 static const struct ethtool_ops xemaclite_ethtool_ops = {
1067 	.get_drvinfo    = xemaclite_ethtools_get_drvinfo,
1068 	.get_link       = ethtool_op_get_link,
1069 	.get_link_ksettings = phy_ethtool_get_link_ksettings,
1070 	.set_link_ksettings = phy_ethtool_set_link_ksettings,
1071 };
1072 
1073 static const struct net_device_ops xemaclite_netdev_ops;
1074 
1075 /**
1076  * xemaclite_of_probe - Probe method for the Emaclite device.
1077  * @ofdev:	Pointer to OF device structure
1078  *
1079  * This function probes for the Emaclite device in the device tree.
1080  * It initializes the driver data structure and the hardware, sets the MAC
1081  * address and registers the network device.
1082  * It also registers a mii_bus for the Emaclite device, if MDIO is included
1083  * in the device.
1084  *
1085  * Return:	0, if the driver is bound to the Emaclite device, or
1086  *		a negative error if there is failure.
1087  */
xemaclite_of_probe(struct platform_device * ofdev)1088 static int xemaclite_of_probe(struct platform_device *ofdev)
1089 {
1090 	struct resource *res;
1091 	struct net_device *ndev = NULL;
1092 	struct net_local *lp = NULL;
1093 	struct device *dev = &ofdev->dev;
1094 
1095 	int rc = 0;
1096 
1097 	dev_info(dev, "Device Tree Probing\n");
1098 
1099 	/* Create an ethernet device instance */
1100 	ndev = alloc_etherdev(sizeof(struct net_local));
1101 	if (!ndev)
1102 		return -ENOMEM;
1103 
1104 	dev_set_drvdata(dev, ndev);
1105 	SET_NETDEV_DEV(ndev, &ofdev->dev);
1106 
1107 	lp = netdev_priv(ndev);
1108 	lp->ndev = ndev;
1109 
1110 	/* Get IRQ for the device */
1111 	rc = platform_get_irq(ofdev, 0);
1112 	if (rc < 0)
1113 		goto error;
1114 
1115 	ndev->irq = rc;
1116 
1117 	res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1118 	lp->base_addr = devm_ioremap_resource(&ofdev->dev, res);
1119 	if (IS_ERR(lp->base_addr)) {
1120 		rc = PTR_ERR(lp->base_addr);
1121 		goto error;
1122 	}
1123 
1124 	ndev->mem_start = res->start;
1125 	ndev->mem_end = res->end;
1126 
1127 	spin_lock_init(&lp->reset_lock);
1128 	lp->next_tx_buf_to_use = 0x0;
1129 	lp->next_rx_buf_to_use = 0x0;
1130 	lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
1131 	lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
1132 
1133 	rc = of_get_ethdev_address(ofdev->dev.of_node, ndev);
1134 	if (rc) {
1135 		dev_warn(dev, "No MAC address found, using random\n");
1136 		eth_hw_addr_random(ndev);
1137 	}
1138 
1139 	/* Clear the Tx CSR's in case this is a restart */
1140 	xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);
1141 	xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
1142 
1143 	/* Set the MAC address in the EmacLite device */
1144 	xemaclite_update_address(lp, ndev->dev_addr);
1145 
1146 	lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
1147 	xemaclite_mdio_setup(lp, &ofdev->dev);
1148 
1149 	dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
1150 
1151 	ndev->netdev_ops = &xemaclite_netdev_ops;
1152 	ndev->ethtool_ops = &xemaclite_ethtool_ops;
1153 	ndev->flags &= ~IFF_MULTICAST;
1154 	ndev->watchdog_timeo = TX_TIMEOUT;
1155 
1156 	/* Finally, register the device */
1157 	rc = register_netdev(ndev);
1158 	if (rc) {
1159 		dev_err(dev,
1160 			"Cannot register network device, aborting\n");
1161 		goto put_node;
1162 	}
1163 
1164 	dev_info(dev,
1165 		 "Xilinx EmacLite at 0x%08lX mapped to 0x%p, irq=%d\n",
1166 		 (unsigned long __force)ndev->mem_start, lp->base_addr, ndev->irq);
1167 	return 0;
1168 
1169 put_node:
1170 	of_node_put(lp->phy_node);
1171 error:
1172 	free_netdev(ndev);
1173 	return rc;
1174 }
1175 
1176 /**
1177  * xemaclite_of_remove - Unbind the driver from the Emaclite device.
1178  * @of_dev:	Pointer to OF device structure
1179  *
1180  * This function is called if a device is physically removed from the system or
1181  * if the driver module is being unloaded. It frees any resources allocated to
1182  * the device.
1183  *
1184  * Return:	0, always.
1185  */
xemaclite_of_remove(struct platform_device * of_dev)1186 static int xemaclite_of_remove(struct platform_device *of_dev)
1187 {
1188 	struct net_device *ndev = platform_get_drvdata(of_dev);
1189 
1190 	struct net_local *lp = netdev_priv(ndev);
1191 
1192 	/* Un-register the mii_bus, if configured */
1193 	if (lp->mii_bus) {
1194 		mdiobus_unregister(lp->mii_bus);
1195 		mdiobus_free(lp->mii_bus);
1196 		lp->mii_bus = NULL;
1197 	}
1198 
1199 	unregister_netdev(ndev);
1200 
1201 	of_node_put(lp->phy_node);
1202 	lp->phy_node = NULL;
1203 
1204 	free_netdev(ndev);
1205 
1206 	return 0;
1207 }
1208 
1209 #ifdef CONFIG_NET_POLL_CONTROLLER
1210 static void
xemaclite_poll_controller(struct net_device * ndev)1211 xemaclite_poll_controller(struct net_device *ndev)
1212 {
1213 	disable_irq(ndev->irq);
1214 	xemaclite_interrupt(ndev->irq, ndev);
1215 	enable_irq(ndev->irq);
1216 }
1217 #endif
1218 
1219 /* Ioctl MII Interface */
xemaclite_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1220 static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1221 {
1222 	if (!dev->phydev || !netif_running(dev))
1223 		return -EINVAL;
1224 
1225 	switch (cmd) {
1226 	case SIOCGMIIPHY:
1227 	case SIOCGMIIREG:
1228 	case SIOCSMIIREG:
1229 		return phy_mii_ioctl(dev->phydev, rq, cmd);
1230 	default:
1231 		return -EOPNOTSUPP;
1232 	}
1233 }
1234 
1235 static const struct net_device_ops xemaclite_netdev_ops = {
1236 	.ndo_open		= xemaclite_open,
1237 	.ndo_stop		= xemaclite_close,
1238 	.ndo_start_xmit		= xemaclite_send,
1239 	.ndo_set_mac_address	= xemaclite_set_mac_address,
1240 	.ndo_tx_timeout		= xemaclite_tx_timeout,
1241 	.ndo_eth_ioctl		= xemaclite_ioctl,
1242 #ifdef CONFIG_NET_POLL_CONTROLLER
1243 	.ndo_poll_controller = xemaclite_poll_controller,
1244 #endif
1245 };
1246 
1247 /* Match table for OF platform binding */
1248 static const struct of_device_id xemaclite_of_match[] = {
1249 	{ .compatible = "xlnx,opb-ethernetlite-1.01.a", },
1250 	{ .compatible = "xlnx,opb-ethernetlite-1.01.b", },
1251 	{ .compatible = "xlnx,xps-ethernetlite-1.00.a", },
1252 	{ .compatible = "xlnx,xps-ethernetlite-2.00.a", },
1253 	{ .compatible = "xlnx,xps-ethernetlite-2.01.a", },
1254 	{ .compatible = "xlnx,xps-ethernetlite-3.00.a", },
1255 	{ /* end of list */ },
1256 };
1257 MODULE_DEVICE_TABLE(of, xemaclite_of_match);
1258 
1259 static struct platform_driver xemaclite_of_driver = {
1260 	.driver = {
1261 		.name = DRIVER_NAME,
1262 		.of_match_table = xemaclite_of_match,
1263 	},
1264 	.probe		= xemaclite_of_probe,
1265 	.remove		= xemaclite_of_remove,
1266 };
1267 
1268 module_platform_driver(xemaclite_of_driver);
1269 
1270 MODULE_AUTHOR("Xilinx, Inc.");
1271 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
1272 MODULE_LICENSE("GPL");
1273