| /openbmc/u-boot/include/synopsys/ |
| H A D | dwcddr21mctl.h | 47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
58 #define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) argument
59 #define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) argument
60 #define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) argument
65 #define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) argument
69 #define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) argument
264 #define DWCDDR21MCTL_MR_BT(x) ((x) << 3) argument
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| /openbmc/u-boot/board/samsung/odroid/ |
| H A D | setup.h | 11 #define SDIV(x) ((x) & 0x7) argument
81 #define MUX_C2C_SEL(x) ((x) & 0x1) argument
91 #define C2C_SEL(x) (((x)) & 0x7) argument
109 #define ACP_RATIO(x) ((x) & 0x7) argument
117 #define DIV_ACP(x) ((x) & 0x1) argument
159 #define UART0_SEL(x) ((x) & 0xf) argument
173 #define DIV_UART0(x) ((x) & 0x1) argument
182 #define MMC0_RATIO(x) ((x) & 0xf) argument
188 #define DIV_MMC0(x) ((x) & 1) argument
205 #define DIV_MMC2(x) ((x) & 0x1) argument
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| /openbmc/linux/drivers/phy/microchip/ |
| H A D | sparx5_serdes_regs.h | 56 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ argument
941 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
943 #define SD10G_LANE_LANE_DF_LOL_GET(x)\ argument
2093 #define SD6G_LANE_LANE_DF_LOL_SET(x)\ argument
2095 #define SD6G_LANE_LANE_DF_LOL_GET(x)\ argument
2374 #define SD_CMU_CMU_45_RESERVED_SET(x)\ argument
2376 #define SD_CMU_CMU_45_RESERVED_GET(x)\ argument
2552 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2554 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2558 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
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| H A D | lan966x_serdes_regs.h | 21 #define HSIO_SD_CFG_PHY_RESET_SET(x)\ argument
23 #define HSIO_SD_CFG_PHY_RESET_GET(x)\ argument
27 #define HSIO_SD_CFG_TX_RESET_SET(x)\ argument
29 #define HSIO_SD_CFG_TX_RESET_GET(x)\ argument
33 #define HSIO_SD_CFG_TX_RATE_SET(x)\ argument
35 #define HSIO_SD_CFG_TX_RATE_GET(x)\ argument
39 #define HSIO_SD_CFG_TX_INVERT_SET(x)\ argument
45 #define HSIO_SD_CFG_TX_EN_SET(x)\ argument
47 #define HSIO_SD_CFG_TX_EN_GET(x)\ argument
57 #define HSIO_SD_CFG_TX_CM_EN_SET(x)\ argument
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
656 #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) argument
657 #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) argument
658 #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) argument
659 #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) argument
660 #define POWER_D1_SCLK_HILEN(x) ((x) << 16) argument
661 #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) argument
662 #define STATIC_SCREEN_HILEN(x) ((x) << 24) argument
663 #define STATIC_SCREEN_LOLEN(x) ((x) << 28) argument
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| H A D | r100d.h | 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
848 #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) argument
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| H A D | r420d.h | 32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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| H A D | rs690d.h | 34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
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| H A D | r300d.h | 84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
92 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
93 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
95 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
96 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
98 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
99 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
101 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
102 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
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| H A D | rs400d.h | 33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
50 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
51 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
53 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
54 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
56 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
57 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
59 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
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| H A D | r520d.h | 41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
54 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) argument
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| H A D | rv250d.h | 32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
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| H A D | rv515d.h | 210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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| /openbmc/u-boot/include/andestech/ |
| H A D | andes_pcu.h | 100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
107 #define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) argument
126 #define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) argument
127 #define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) argument
129 #define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) argument
132 #define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) argument
133 #define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) argument
134 #define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) argument
135 #define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) argument
137 #define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) argument
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| /openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_main_regs.h | 65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
4415 #define FDMA_CTRL_NRESET_SET(x)\ argument
4417 #define FDMA_CTRL_NRESET_GET(x)\ argument
4443 #define GCB_CHIP_ID_ONE_SET(x)\ argument
4445 #define GCB_CHIP_ID_ONE_GET(x)\ argument
6319 #define QS_INJ_CTRL_EOF_SET(x)\ argument
6321 #define QS_INJ_CTRL_EOF_GET(x)\ argument
6325 #define QS_INJ_CTRL_SOF_SET(x)\ argument
6327 #define QS_INJ_CTRL_SOF_GET(x)\ argument
6391 #define QSYS_ATOP_ATOP_SET(x)\ argument
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| /openbmc/linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_regs.h | 14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
129 #define VEPU_REG_CHECKPOINT_RESULT(x) \ argument
198 #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) argument
257 #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) argument
280 #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) argument
320 #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) argument
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| H A D | hantro_g1_regs.h | 28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument
101 #define G1_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7) argument
102 #define G1_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4) argument
111 #define G1_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8) argument
146 #define G1_REG_DEC_CTRL4_DQ_EDGES(x) (((x) & 0xf) << 20) argument
153 #define G1_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8) argument
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| /openbmc/linux/drivers/net/ethernet/microchip/lan966x/ |
| H A D | lan966x_regs.h | 74 #define ANA_ANAINTR_INTR_SET(x)\ argument
76 #define ANA_ANAINTR_INTR_GET(x)\ argument
80 #define ANA_ANAINTR_INTR_ENA_SET(x)\ argument
164 #define ANA_PGID_PGID_SET(x)\ argument
166 #define ANA_PGID_PGID_GET(x)\ argument
1067 #define PTP_DOM_CFG_ENA_SET(x)\ argument
1069 #define PTP_DOM_CFG_ENA_GET(x)\ argument
1239 #define QS_INJ_CTRL_EOF_SET(x)\ argument
1241 #define QS_INJ_CTRL_EOF_GET(x)\ argument
1245 #define QS_INJ_CTRL_SOF_SET(x)\ argument
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| /openbmc/linux/tools/lib/bpf/ |
| H A D | bpf_endian.h | 64 # define __bpf_ntohs(x) (x) argument
65 # define __bpf_htons(x) (x) argument
68 # define __bpf_ntohl(x) (x) argument
69 # define __bpf_htonl(x) (x) argument
72 # define __bpf_be64_to_cpu(x) (x) argument
80 #define bpf_htons(x) \ argument
83 #define bpf_ntohs(x) \ argument
86 #define bpf_htonl(x) \ argument
89 #define bpf_ntohl(x) \ argument
92 #define bpf_cpu_to_be64(x) \ argument
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| /openbmc/linux/include/soc/mscc/ |
| H A D | ocelot_ana.h | 19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument
64 #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) argument
76 #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) argument
99 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) argument
108 #define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0)) argument
116 #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) argument
130 #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0)) argument
144 #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0)) argument
162 #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0)) argument
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | opcodes.h | 24 #define ___asm_opcode_swab32(x) ( \ argument
30 #define ___asm_opcode_swab16(x) ( \ argument
34 #define ___asm_opcode_swahb32(x) ( \ argument
38 #define ___asm_opcode_swahw32(x) ( \ argument
88 #define ___opcode_swab32(x) swab32(x) argument
89 #define ___opcode_swab16(x) swab16(x) argument
90 #define ___opcode_swahb32(x) swahb32(x) argument
134 #define __opcode_is_thumb32(x) ( \ argument
138 #define __opcode_is_thumb16(x) ( \ argument
218 #define ___inst_arm(x) .long x argument
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | opcodes.h | 24 #define ___asm_opcode_swab32(x) ( \ argument
30 #define ___asm_opcode_swab16(x) ( \ argument
34 #define ___asm_opcode_swahb32(x) ( \ argument
38 #define ___asm_opcode_swahw32(x) ( \ argument
88 #define ___opcode_swab32(x) swab32(x) argument
89 #define ___opcode_swab16(x) swab16(x) argument
90 #define ___opcode_swahb32(x) swahb32(x) argument
91 #define ___opcode_swahw32(x) swahw32(x) argument
92 #define ___opcode_identity32(x) ((u32)(x)) argument
139 #define __opcode_is_thumb32(x) ( \ argument
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| /openbmc/u-boot/include/linux/byteorder/ |
| H A D | little_endian.h | 32 #define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) argument
33 #define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) argument
34 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) argument
35 #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) argument
36 #define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) argument
99 #define __cpu_to_be64s(x) __swab64s((x)) argument
100 #define __be64_to_cpus(x) __swab64s((x)) argument
101 #define __cpu_to_be32s(x) __swab32s((x)) argument
102 #define __be32_to_cpus(x) __swab32s((x)) argument
103 #define __cpu_to_be16s(x) __swab16s((x)) argument
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| H A D | big_endian.h | 16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
38 #define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) argument
93 #define __cpu_to_le64s(x) __swab64s((x)) argument
94 #define __le64_to_cpus(x) __swab64s((x)) argument
95 #define __cpu_to_le32s(x) __swab32s((x)) argument
96 #define __le32_to_cpus(x) __swab32s((x)) argument
97 #define __cpu_to_le16s(x) __swab16s((x)) argument
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| /openbmc/linux/include/uapi/linux/byteorder/ |
| H A D | big_endian.h | 16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
38 #define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) argument
93 #define __cpu_to_le64s(x) __swab64s((x)) argument
94 #define __le64_to_cpus(x) __swab64s((x)) argument
95 #define __cpu_to_le32s(x) __swab32s((x)) argument
96 #define __le32_to_cpus(x) __swab32s((x)) argument
97 #define __cpu_to_le16s(x) __swab16s((x)) argument
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