1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
10 */
11
12 #include <common.h>
13 #include <asm/arch/pxa-regs.h>
14 #include <asm/io.h>
15 #include <asm/system.h>
16 #include <command.h>
17
18 /* Flush I/D-cache */
cache_flush(void)19 static void cache_flush(void)
20 {
21 unsigned long i = 0;
22
23 asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
24 }
25
cleanup_before_linux(void)26 int cleanup_before_linux(void)
27 {
28 /*
29 * This function is called just before we call Linux. It prepares
30 * the processor for Linux by just disabling everything that can
31 * disturb booting Linux.
32 */
33
34 disable_interrupts();
35 icache_disable();
36 dcache_disable();
37 cache_flush();
38
39 return 0;
40 }
41
pxa_wait_ticks(int ticks)42 void pxa_wait_ticks(int ticks)
43 {
44 writel(0, OSCR);
45 while (readl(OSCR) < ticks)
46 asm volatile("" : : : "memory");
47 }
48
writelrb(uint32_t val,uint32_t addr)49 inline void writelrb(uint32_t val, uint32_t addr)
50 {
51 writel(val, addr);
52 asm volatile("" : : : "memory");
53 readl(addr);
54 asm volatile("" : : : "memory");
55 }
56
pxa2xx_dram_init(void)57 void pxa2xx_dram_init(void)
58 {
59 uint32_t tmp;
60 int i;
61 /*
62 * 1) Initialize Asynchronous static memory controller
63 */
64
65 writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
66 writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
67 writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
68 /*
69 * 2) Initialize Card Interface
70 */
71
72 /* MECR: Memory Expansion Card Register */
73 writelrb(CONFIG_SYS_MECR_VAL, MECR);
74 /* MCMEM0: Card Interface slot 0 timing */
75 writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
76 /* MCMEM1: Card Interface slot 1 timing */
77 writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
78 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
79 writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
80 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
81 writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
82 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
83 writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
84 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
85 writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
86
87 /*
88 * 3) Configure Fly-By DMA register
89 */
90
91 writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
92
93 /*
94 * 4) Initialize Timing for Sync Memory (SDCLK0)
95 */
96
97 /*
98 * Before accessing MDREFR we need a valid DRI field, so we set
99 * this to power on defaults + DRI field.
100 */
101
102 /* Read current MDREFR config and zero out DRI */
103 tmp = readl(MDREFR) & ~0xfff;
104 /* Add user-specified DRI */
105 tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
106 /* Configure important bits */
107 tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
108 tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
109
110 /* Write MDREFR back */
111 writelrb(tmp, MDREFR);
112
113 /*
114 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
115 */
116
117 /* Initialize SXCNFG register. Assert the enable bits.
118 *
119 * Write SXMRS to cause an MRS command to all enabled banks of
120 * synchronous static memory. Note that SXLCR need not be written
121 * at this time.
122 */
123 writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
124
125 /*
126 * 6) Initialize SDRAM
127 */
128
129 writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
130 writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
131
132 /*
133 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
134 * but not enable each SDRAM partition pair.
135 */
136
137 writelrb(CONFIG_SYS_MDCNFG_VAL &
138 ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
139 /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
140 pxa_wait_ticks(0x300);
141
142 /*
143 * 8) Trigger a number (usually 8) refresh cycles by attempting
144 * non-burst read or write accesses to disabled SDRAM, as commonly
145 * specified in the power up sequence documented in SDRAM data
146 * sheets. The address(es) used for this purpose must not be
147 * cacheable.
148 */
149 for (i = 9; i >= 0; i--) {
150 writel(i, 0xa0000000);
151 asm volatile("" : : : "memory");
152 }
153 /*
154 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
155 */
156
157 tmp = CONFIG_SYS_MDCNFG_VAL &
158 (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
159 tmp |= readl(MDCNFG);
160 writelrb(tmp, MDCNFG);
161
162 /*
163 * 10) Write MDMRS.
164 */
165
166 writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
167
168 /*
169 * 11) Enable APD
170 */
171
172 if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
173 tmp = readl(MDREFR);
174 tmp |= MDREFR_APD;
175 writelrb(tmp, MDREFR);
176 }
177 }
178
pxa_gpio_setup(void)179 void pxa_gpio_setup(void)
180 {
181 writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
182 writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
183 writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
184 #if defined(CONFIG_CPU_PXA27X)
185 writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
186 #endif
187
188 writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
189 writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
190 writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
191 #if defined(CONFIG_CPU_PXA27X)
192 writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
193 #endif
194
195 writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
196 writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
197 writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
198 #if defined(CONFIG_CPU_PXA27X)
199 writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
200 #endif
201
202 writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
203 writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
204 writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
205 writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
206 writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
207 writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
208 #if defined(CONFIG_CPU_PXA27X)
209 writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
210 writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
211 #endif
212
213 writel(CONFIG_SYS_PSSR_VAL, PSSR);
214 }
215
pxa_interrupt_setup(void)216 void pxa_interrupt_setup(void)
217 {
218 writel(0, ICLR);
219 writel(0, ICMR);
220 #if defined(CONFIG_CPU_PXA27X)
221 writel(0, ICLR2);
222 writel(0, ICMR2);
223 #endif
224 }
225
pxa_clock_setup(void)226 void pxa_clock_setup(void)
227 {
228 writel(CONFIG_SYS_CKEN, CKEN);
229 writel(CONFIG_SYS_CCCR, CCCR);
230 asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
231
232 /* enable the 32Khz oscillator for RTC and PowerManager */
233 writel(OSCC_OON, OSCC);
234 while (!(readl(OSCC) & OSCC_OOK))
235 asm volatile("" : : : "memory");
236 }
237
pxa_wakeup(void)238 void pxa_wakeup(void)
239 {
240 uint32_t rcsr;
241
242 rcsr = readl(RCSR);
243 writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
244
245 /* Wakeup */
246 if (rcsr & RCSR_SMR) {
247 writel(PSSR_PH, PSSR);
248 pxa2xx_dram_init();
249 icache_disable();
250 dcache_disable();
251 asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
252 }
253 }
254
arch_cpu_init(void)255 int arch_cpu_init(void)
256 {
257 pxa_gpio_setup();
258 pxa_wakeup();
259 pxa_interrupt_setup();
260 pxa_clock_setup();
261 return 0;
262 }
263
i2c_clk_enable(void)264 void i2c_clk_enable(void)
265 {
266 /* Set the global I2C clock on */
267 writel(readl(CKEN) | CKEN14_I2C, CKEN);
268 }
269
270 void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
271
reset_cpu(ulong ignored)272 void reset_cpu(ulong ignored)
273 {
274 uint32_t tmp;
275
276 setbits_le32(OWER, OWER_WME);
277
278 tmp = readl(OSCR);
279 tmp += 0x1000;
280 writel(tmp, OSMR3);
281 writel(MDREFR_SLFRSH, MDREFR);
282
283 for (;;)
284 ;
285 }
286
enable_caches(void)287 void enable_caches(void)
288 {
289 #ifndef CONFIG_SYS_ICACHE_OFF
290 icache_enable();
291 #endif
292 #ifndef CONFIG_SYS_DCACHE_OFF
293 dcache_enable();
294 #endif
295 }
296