xref: /openbmc/linux/drivers/i2c/busses/i2c-mpc.c (revision 59738ab2)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * This is a combined i2c adapter and algorithm driver for the
4  * MPC107/Tsi107 PowerPC northbridge and processors that include
5  * the same I2C unit (8240, 8245, 85xx).
6  *
7  * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
8  * Copyright (C) 2021 Allied Telesis Labs
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched/signal.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/slab.h>
20 
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 
29 #include <asm/mpc52xx.h>
30 #include <asm/mpc85xx.h>
31 #include <sysdev/fsl_soc.h>
32 
33 #define DRV_NAME "mpc-i2c"
34 
35 #define MPC_I2C_CLOCK_LEGACY   0
36 #define MPC_I2C_CLOCK_PRESERVE (~0U)
37 
38 #define MPC_I2C_FDR   0x04
39 #define MPC_I2C_CR    0x08
40 #define MPC_I2C_SR    0x0c
41 #define MPC_I2C_DR    0x10
42 #define MPC_I2C_DFSRR 0x14
43 
44 #define CCR_MEN  0x80
45 #define CCR_MIEN 0x40
46 #define CCR_MSTA 0x20
47 #define CCR_MTX  0x10
48 #define CCR_TXAK 0x08
49 #define CCR_RSTA 0x04
50 #define CCR_RSVD 0x02
51 
52 #define CSR_MCF  0x80
53 #define CSR_MAAS 0x40
54 #define CSR_MBB  0x20
55 #define CSR_MAL  0x10
56 #define CSR_SRW  0x04
57 #define CSR_MIF  0x02
58 #define CSR_RXAK 0x01
59 
60 enum mpc_i2c_action {
61 	MPC_I2C_ACTION_START = 1,
62 	MPC_I2C_ACTION_RESTART,
63 	MPC_I2C_ACTION_READ_BEGIN,
64 	MPC_I2C_ACTION_READ_BYTE,
65 	MPC_I2C_ACTION_WRITE,
66 	MPC_I2C_ACTION_STOP,
67 
68 	__MPC_I2C_ACTION_CNT
69 };
70 
71 static const char * const action_str[] = {
72 	"invalid",
73 	"start",
74 	"restart",
75 	"read begin",
76 	"read",
77 	"write",
78 	"stop",
79 };
80 
81 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
82 
83 struct mpc_i2c {
84 	struct device *dev;
85 	void __iomem *base;
86 	u32 interrupt;
87 	wait_queue_head_t waitq;
88 	spinlock_t lock;
89 	struct i2c_adapter adap;
90 	int irq;
91 	u32 real_clk;
92 	u8 fdr, dfsrr;
93 	struct clk *clk_per;
94 	u32 cntl_bits;
95 	enum mpc_i2c_action action;
96 	struct i2c_msg *msgs;
97 	int num_msgs;
98 	int curr_msg;
99 	u32 byte_posn;
100 	u32 block;
101 	int rc;
102 	int expect_rxack;
103 	bool has_errata_A004447;
104 };
105 
106 struct mpc_i2c_divider {
107 	u16 divider;
108 	u16 fdr;	/* including dfsrr */
109 };
110 
111 struct mpc_i2c_data {
112 	void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
113 };
114 
writeccr(struct mpc_i2c * i2c,u32 x)115 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
116 {
117 	writeb(x, i2c->base + MPC_I2C_CR);
118 }
119 
120 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
121  * the bus, because it wants to send ACK.
122  * Following sequence of enabling/disabling and sending start/stop generates
123  * the 9 pulses, each with a START then ending with STOP, so it's all OK.
124  */
mpc_i2c_fixup(struct mpc_i2c * i2c)125 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
126 {
127 	int k;
128 	unsigned long flags;
129 
130 	for (k = 9; k; k--) {
131 		writeccr(i2c, 0);
132 		writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
133 		writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
134 		readb(i2c->base + MPC_I2C_DR); /* init xfer */
135 		udelay(15); /* let it hit the bus */
136 		local_irq_save(flags); /* should not be delayed further */
137 		writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
138 		readb(i2c->base + MPC_I2C_DR);
139 		if (k != 1)
140 			udelay(5);
141 		local_irq_restore(flags);
142 	}
143 	writeccr(i2c, CCR_MEN); /* Initiate STOP */
144 	readb(i2c->base + MPC_I2C_DR);
145 	udelay(15); /* Let STOP propagate */
146 	writeccr(i2c, 0);
147 }
148 
i2c_mpc_wait_sr(struct mpc_i2c * i2c,int mask)149 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
150 {
151 	void __iomem *addr = i2c->base + MPC_I2C_SR;
152 	u8 val;
153 
154 	return readb_poll_timeout(addr, val, val & mask, 0, 100);
155 }
156 
157 /*
158  * Workaround for Erratum A004447. From the P2040CE Rev Q
159  *
160  * 1.  Set up the frequency divider and sampling rate.
161  * 2.  I2CCR - a0h
162  * 3.  Poll for I2CSR[MBB] to get set.
163  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
164  *     step 5. If MAL is not set, then go to step 13.
165  * 5.  I2CCR - 00h
166  * 6.  I2CCR - 22h
167  * 7.  I2CCR - a2h
168  * 8.  Poll for I2CSR[MBB] to get set.
169  * 9.  Issue read to I2CDR.
170  * 10. Poll for I2CSR[MIF] to be set.
171  * 11. I2CCR - 82h
172  * 12. Workaround complete. Skip the next steps.
173  * 13. Issue read to I2CDR.
174  * 14. Poll for I2CSR[MIF] to be set.
175  * 15. I2CCR - 80h
176  */
mpc_i2c_fixup_A004447(struct mpc_i2c * i2c)177 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
178 {
179 	int ret;
180 	u32 val;
181 
182 	writeccr(i2c, CCR_MEN | CCR_MSTA);
183 	ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
184 	if (ret) {
185 		dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
186 		return;
187 	}
188 
189 	val = readb(i2c->base + MPC_I2C_SR);
190 
191 	if (val & CSR_MAL) {
192 		writeccr(i2c, 0x00);
193 		writeccr(i2c, CCR_MSTA | CCR_RSVD);
194 		writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
195 		ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
196 		if (ret) {
197 			dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
198 			return;
199 		}
200 		val = readb(i2c->base + MPC_I2C_DR);
201 		ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
202 		if (ret) {
203 			dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
204 			return;
205 		}
206 		writeccr(i2c, CCR_MEN | CCR_RSVD);
207 	} else {
208 		val = readb(i2c->base + MPC_I2C_DR);
209 		ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
210 		if (ret) {
211 			dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
212 			return;
213 		}
214 		writeccr(i2c, CCR_MEN);
215 	}
216 }
217 
218 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
219 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
220 	{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
221 	{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
222 	{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
223 	{52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
224 	{68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
225 	{96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
226 	{128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
227 	{176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
228 	{240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
229 	{320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
230 	{448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
231 	{640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
232 	{1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
233 	{1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
234 	{2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
235 	{4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
236 	{7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
237 	{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
238 };
239 
mpc_i2c_get_fdr_52xx(struct device_node * node,u32 clock,u32 * real_clk)240 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
241 					  u32 *real_clk)
242 {
243 	struct fwnode_handle *fwnode = of_fwnode_handle(node);
244 	const struct mpc_i2c_divider *div = NULL;
245 	unsigned int pvr = mfspr(SPRN_PVR);
246 	u32 divider;
247 	int i;
248 
249 	if (clock == MPC_I2C_CLOCK_LEGACY) {
250 		/* see below - default fdr = 0x3f -> div = 2048 */
251 		*real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / 2048;
252 		return -EINVAL;
253 	}
254 
255 	/* Determine divider value */
256 	divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
257 
258 	/*
259 	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
260 	 * is equal to or lower than the requested speed.
261 	 */
262 	for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
263 		div = &mpc_i2c_dividers_52xx[i];
264 		/* Old MPC5200 rev A CPUs do not support the high bits */
265 		if (div->fdr & 0xc0 && pvr == 0x80822011)
266 			continue;
267 		if (div->divider >= divider)
268 			break;
269 	}
270 
271 	*real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
272 	return (int)div->fdr;
273 }
274 
mpc_i2c_setup_52xx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)275 static void mpc_i2c_setup_52xx(struct device_node *node,
276 					 struct mpc_i2c *i2c,
277 					 u32 clock)
278 {
279 	int ret, fdr;
280 
281 	if (clock == MPC_I2C_CLOCK_PRESERVE) {
282 		dev_dbg(i2c->dev, "using fdr %d\n",
283 			readb(i2c->base + MPC_I2C_FDR));
284 		return;
285 	}
286 
287 	ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
288 	fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
289 
290 	writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
291 
292 	if (ret >= 0)
293 		dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
294 			 fdr);
295 }
296 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
mpc_i2c_setup_52xx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)297 static void mpc_i2c_setup_52xx(struct device_node *node,
298 					 struct mpc_i2c *i2c,
299 					 u32 clock)
300 {
301 }
302 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
303 
304 #ifdef CONFIG_PPC_MPC512x
mpc_i2c_setup_512x(struct device_node * node,struct mpc_i2c * i2c,u32 clock)305 static void mpc_i2c_setup_512x(struct device_node *node,
306 					 struct mpc_i2c *i2c,
307 					 u32 clock)
308 {
309 	struct device_node *node_ctrl;
310 	void __iomem *ctrl;
311 	u32 idx;
312 
313 	/* Enable I2C interrupts for mpc5121 */
314 	node_ctrl = of_find_compatible_node(NULL, NULL,
315 					    "fsl,mpc5121-i2c-ctrl");
316 	if (node_ctrl) {
317 		ctrl = of_iomap(node_ctrl, 0);
318 		if (ctrl) {
319 			u64 addr;
320 			/* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
321 			of_property_read_reg(node, 0, &addr, NULL);
322 			idx = (addr & 0xff) / 0x20;
323 			setbits32(ctrl, 1 << (24 + idx * 2));
324 			iounmap(ctrl);
325 		}
326 		of_node_put(node_ctrl);
327 	}
328 
329 	/* The clock setup for the 52xx works also fine for the 512x */
330 	mpc_i2c_setup_52xx(node, i2c, clock);
331 }
332 #else /* CONFIG_PPC_MPC512x */
mpc_i2c_setup_512x(struct device_node * node,struct mpc_i2c * i2c,u32 clock)333 static void mpc_i2c_setup_512x(struct device_node *node,
334 					 struct mpc_i2c *i2c,
335 					 u32 clock)
336 {
337 }
338 #endif /* CONFIG_PPC_MPC512x */
339 
340 #ifdef CONFIG_FSL_SOC
341 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
342 	{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
343 	{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
344 	{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
345 	{544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
346 	{672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
347 	{800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
348 	{1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
349 	{1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
350 	{1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
351 	{2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
352 	{3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
353 	{4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
354 	{7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
355 	{12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
356 	{18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
357 	{30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
358 	{49152, 0x011e}, {61440, 0x011f}
359 };
360 
mpc_i2c_get_sec_cfg_8xxx(void)361 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
362 {
363 	struct device_node *node;
364 	u32 __iomem *reg;
365 	u32 val = 0;
366 
367 	node = of_find_node_by_name(NULL, "global-utilities");
368 	if (node) {
369 		const u32 *prop = of_get_property(node, "reg", NULL);
370 		if (prop) {
371 			/*
372 			 * Map and check POR Device Status Register 2
373 			 * (PORDEVSR2) at 0xE0014. Note than while MPC8533
374 			 * and MPC8544 indicate SEC frequency ratio
375 			 * configuration as bit 26 in PORDEVSR2, other MPC8xxx
376 			 * parts may store it differently or may not have it
377 			 * at all.
378 			 */
379 			reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
380 			if (!reg)
381 				printk(KERN_ERR
382 				       "Error: couldn't map PORDEVSR2\n");
383 			else
384 				val = in_be32(reg) & 0x00000020; /* sec-cfg */
385 			iounmap(reg);
386 		}
387 	}
388 	of_node_put(node);
389 
390 	return val;
391 }
392 
mpc_i2c_get_prescaler_8xxx(void)393 static u32 mpc_i2c_get_prescaler_8xxx(void)
394 {
395 	/*
396 	 * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
397 	 * may have prescaler 1, 2, or 3, depending on the power-on
398 	 * configuration.
399 	 */
400 	u32 prescaler = 1;
401 
402 	/* mpc85xx */
403 	if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
404 		|| pvr_version_is(PVR_VER_E500MC)
405 		|| pvr_version_is(PVR_VER_E5500)
406 		|| pvr_version_is(PVR_VER_E6500)) {
407 		unsigned int svr = mfspr(SPRN_SVR);
408 
409 		if ((SVR_SOC_VER(svr) == SVR_8540)
410 			|| (SVR_SOC_VER(svr) == SVR_8541)
411 			|| (SVR_SOC_VER(svr) == SVR_8560)
412 			|| (SVR_SOC_VER(svr) == SVR_8555)
413 			|| (SVR_SOC_VER(svr) == SVR_8610))
414 			/* the above 85xx SoCs have prescaler 1 */
415 			prescaler = 1;
416 		else if ((SVR_SOC_VER(svr) == SVR_8533)
417 			|| (SVR_SOC_VER(svr) == SVR_8544))
418 			/* the above 85xx SoCs have prescaler 3 or 2 */
419 			prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
420 		else
421 			/* all the other 85xx have prescaler 2 */
422 			prescaler = 2;
423 	}
424 
425 	return prescaler;
426 }
427 
mpc_i2c_get_fdr_8xxx(struct device_node * node,u32 clock,u32 * real_clk)428 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
429 					  u32 *real_clk)
430 {
431 	const struct mpc_i2c_divider *div = NULL;
432 	u32 prescaler = mpc_i2c_get_prescaler_8xxx();
433 	u32 divider;
434 	int i;
435 
436 	if (clock == MPC_I2C_CLOCK_LEGACY) {
437 		/* see below - default fdr = 0x1031 -> div = 16 * 3072 */
438 		*real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
439 		return -EINVAL;
440 	}
441 
442 	divider = fsl_get_sys_freq() / clock / prescaler;
443 
444 	pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
445 		 fsl_get_sys_freq(), clock, divider);
446 
447 	/*
448 	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
449 	 * is equal to or lower than the requested speed.
450 	 */
451 	for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
452 		div = &mpc_i2c_dividers_8xxx[i];
453 		if (div->divider >= divider)
454 			break;
455 	}
456 
457 	*real_clk = fsl_get_sys_freq() / prescaler / div->divider;
458 	return (int)div->fdr;
459 }
460 
mpc_i2c_setup_8xxx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)461 static void mpc_i2c_setup_8xxx(struct device_node *node,
462 					 struct mpc_i2c *i2c,
463 					 u32 clock)
464 {
465 	int ret, fdr;
466 
467 	if (clock == MPC_I2C_CLOCK_PRESERVE) {
468 		dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
469 			readb(i2c->base + MPC_I2C_DFSRR),
470 			readb(i2c->base + MPC_I2C_FDR));
471 		return;
472 	}
473 
474 	ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
475 	fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
476 
477 	writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
478 	writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
479 
480 	if (ret >= 0)
481 		dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
482 			 i2c->real_clk, fdr >> 8, fdr & 0xff);
483 }
484 
485 #else /* !CONFIG_FSL_SOC */
mpc_i2c_setup_8xxx(struct device_node * node,struct mpc_i2c * i2c,u32 clock)486 static void mpc_i2c_setup_8xxx(struct device_node *node,
487 					 struct mpc_i2c *i2c,
488 					 u32 clock)
489 {
490 }
491 #endif /* CONFIG_FSL_SOC */
492 
mpc_i2c_finish(struct mpc_i2c * i2c,int rc)493 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
494 {
495 	i2c->rc = rc;
496 	i2c->block = 0;
497 	i2c->cntl_bits = CCR_MEN;
498 	writeccr(i2c, i2c->cntl_bits);
499 	wake_up(&i2c->waitq);
500 }
501 
mpc_i2c_do_action(struct mpc_i2c * i2c)502 static void mpc_i2c_do_action(struct mpc_i2c *i2c)
503 {
504 	struct i2c_msg *msg = NULL;
505 	int dir = 0;
506 	int recv_len = 0;
507 	u8 byte;
508 
509 	dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
510 
511 	i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
512 
513 	if (i2c->action != MPC_I2C_ACTION_STOP) {
514 		msg = &i2c->msgs[i2c->curr_msg];
515 		if (msg->flags & I2C_M_RD)
516 			dir = 1;
517 		if (msg->flags & I2C_M_RECV_LEN)
518 			recv_len = 1;
519 	}
520 
521 	switch (i2c->action) {
522 	case MPC_I2C_ACTION_RESTART:
523 		i2c->cntl_bits |= CCR_RSTA;
524 		fallthrough;
525 
526 	case MPC_I2C_ACTION_START:
527 		i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
528 		writeccr(i2c, i2c->cntl_bits);
529 		writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
530 		i2c->expect_rxack = 1;
531 		i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
532 		break;
533 
534 	case MPC_I2C_ACTION_READ_BEGIN:
535 		if (msg->len) {
536 			if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
537 				i2c->cntl_bits |= CCR_TXAK;
538 
539 			writeccr(i2c, i2c->cntl_bits);
540 			/* Dummy read */
541 			readb(i2c->base + MPC_I2C_DR);
542 		}
543 		i2c->action = MPC_I2C_ACTION_READ_BYTE;
544 		break;
545 
546 	case MPC_I2C_ACTION_READ_BYTE:
547 		if (i2c->byte_posn || !recv_len) {
548 			/* Generate Tx ACK on next to last byte */
549 			if (i2c->byte_posn == msg->len - 2)
550 				i2c->cntl_bits |= CCR_TXAK;
551 			/* Do not generate stop on last byte */
552 			if (i2c->byte_posn == msg->len - 1)
553 				i2c->cntl_bits |= CCR_MTX;
554 
555 			writeccr(i2c, i2c->cntl_bits);
556 		}
557 
558 		byte = readb(i2c->base + MPC_I2C_DR);
559 
560 		if (i2c->byte_posn == 0 && recv_len) {
561 			if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
562 				mpc_i2c_finish(i2c, -EPROTO);
563 				return;
564 			}
565 			msg->len += byte;
566 			/*
567 			 * For block reads, generate Tx ACK here if data length
568 			 * is 1 byte (total length is 2 bytes).
569 			 */
570 			if (msg->len == 2) {
571 				i2c->cntl_bits |= CCR_TXAK;
572 				writeccr(i2c, i2c->cntl_bits);
573 			}
574 		}
575 
576 		dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
577 		msg->buf[i2c->byte_posn++] = byte;
578 		break;
579 
580 	case MPC_I2C_ACTION_WRITE:
581 		dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
582 			msg->buf[i2c->byte_posn]);
583 		writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
584 		i2c->expect_rxack = 1;
585 		break;
586 
587 	case MPC_I2C_ACTION_STOP:
588 		mpc_i2c_finish(i2c, 0);
589 		break;
590 
591 	default:
592 		WARN(1, "Unexpected action %d\n", i2c->action);
593 		break;
594 	}
595 
596 	if (msg && msg->len == i2c->byte_posn) {
597 		i2c->curr_msg++;
598 		i2c->byte_posn = 0;
599 
600 		if (i2c->curr_msg == i2c->num_msgs) {
601 			i2c->action = MPC_I2C_ACTION_STOP;
602 			/*
603 			 * We don't get another interrupt on read so
604 			 * finish the transfer now
605 			 */
606 			if (dir)
607 				mpc_i2c_finish(i2c, 0);
608 		} else {
609 			i2c->action = MPC_I2C_ACTION_RESTART;
610 		}
611 	}
612 }
613 
mpc_i2c_do_intr(struct mpc_i2c * i2c,u8 status)614 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
615 {
616 	spin_lock(&i2c->lock);
617 
618 	if (!(status & CSR_MCF)) {
619 		dev_dbg(i2c->dev, "unfinished\n");
620 		mpc_i2c_finish(i2c, -EIO);
621 		goto out;
622 	}
623 
624 	if (status & CSR_MAL) {
625 		dev_dbg(i2c->dev, "arbitration lost\n");
626 		mpc_i2c_finish(i2c, -EAGAIN);
627 		goto out;
628 	}
629 
630 	if (i2c->expect_rxack && (status & CSR_RXAK)) {
631 		dev_dbg(i2c->dev, "no Rx ACK\n");
632 		mpc_i2c_finish(i2c, -ENXIO);
633 		goto out;
634 	}
635 	i2c->expect_rxack = 0;
636 
637 	mpc_i2c_do_action(i2c);
638 
639 out:
640 	spin_unlock(&i2c->lock);
641 }
642 
mpc_i2c_isr(int irq,void * dev_id)643 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
644 {
645 	struct mpc_i2c *i2c = dev_id;
646 	u8 status;
647 
648 	status = readb(i2c->base + MPC_I2C_SR);
649 	if (status & CSR_MIF) {
650 		/* Wait up to 100us for transfer to properly complete */
651 		readb_poll_timeout_atomic(i2c->base + MPC_I2C_SR, status, status & CSR_MCF, 0, 100);
652 		writeb(0, i2c->base + MPC_I2C_SR);
653 		mpc_i2c_do_intr(i2c, status);
654 		return IRQ_HANDLED;
655 	}
656 	return IRQ_NONE;
657 }
658 
mpc_i2c_wait_for_completion(struct mpc_i2c * i2c)659 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
660 {
661 	long time_left;
662 
663 	time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
664 	if (!time_left)
665 		return -ETIMEDOUT;
666 	if (time_left < 0)
667 		return time_left;
668 
669 	return 0;
670 }
671 
mpc_i2c_execute_msg(struct mpc_i2c * i2c)672 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
673 {
674 	unsigned long orig_jiffies;
675 	unsigned long flags;
676 	int ret;
677 
678 	spin_lock_irqsave(&i2c->lock, flags);
679 
680 	i2c->curr_msg = 0;
681 	i2c->rc = 0;
682 	i2c->byte_posn = 0;
683 	i2c->block = 1;
684 	i2c->action = MPC_I2C_ACTION_START;
685 
686 	i2c->cntl_bits = CCR_MEN | CCR_MIEN;
687 	writeb(0, i2c->base + MPC_I2C_SR);
688 	writeccr(i2c, i2c->cntl_bits);
689 
690 	mpc_i2c_do_action(i2c);
691 
692 	spin_unlock_irqrestore(&i2c->lock, flags);
693 
694 	ret = mpc_i2c_wait_for_completion(i2c);
695 	if (ret)
696 		i2c->rc = ret;
697 
698 	if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
699 		i2c_recover_bus(&i2c->adap);
700 
701 	orig_jiffies = jiffies;
702 	/* Wait until STOP is seen, allow up to 1 s */
703 	while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
704 		if (time_after(jiffies, orig_jiffies + HZ)) {
705 			u8 status = readb(i2c->base + MPC_I2C_SR);
706 
707 			dev_dbg(i2c->dev, "timeout\n");
708 			if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
709 				writeb(status & ~CSR_MAL,
710 				       i2c->base + MPC_I2C_SR);
711 				i2c_recover_bus(&i2c->adap);
712 			}
713 			return -EIO;
714 		}
715 		cond_resched();
716 	}
717 
718 	return i2c->rc;
719 }
720 
mpc_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)721 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
722 {
723 	int rc, ret = num;
724 	struct mpc_i2c *i2c = i2c_get_adapdata(adap);
725 	int i;
726 
727 	dev_dbg(i2c->dev, "num = %d\n", num);
728 	for (i = 0; i < num; i++)
729 		dev_dbg(i2c->dev, "  addr = %02x, flags = %02x, len = %d, %*ph\n",
730 			msgs[i].addr, msgs[i].flags, msgs[i].len,
731 			msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
732 			msgs[i].buf);
733 
734 	WARN_ON(i2c->msgs != NULL);
735 	i2c->msgs = msgs;
736 	i2c->num_msgs = num;
737 
738 	rc = mpc_i2c_execute_msg(i2c);
739 	if (rc < 0)
740 		ret = rc;
741 
742 	i2c->num_msgs = 0;
743 	i2c->msgs = NULL;
744 
745 	return ret;
746 }
747 
mpc_functionality(struct i2c_adapter * adap)748 static u32 mpc_functionality(struct i2c_adapter *adap)
749 {
750 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
751 	  | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
752 }
753 
fsl_i2c_bus_recovery(struct i2c_adapter * adap)754 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
755 {
756 	struct mpc_i2c *i2c = i2c_get_adapdata(adap);
757 
758 	if (i2c->has_errata_A004447)
759 		mpc_i2c_fixup_A004447(i2c);
760 	else
761 		mpc_i2c_fixup(i2c);
762 
763 	return 0;
764 }
765 
766 static const struct i2c_algorithm mpc_algo = {
767 	.master_xfer = mpc_xfer,
768 	.functionality = mpc_functionality,
769 };
770 
771 static struct i2c_adapter mpc_ops = {
772 	.owner = THIS_MODULE,
773 	.algo = &mpc_algo,
774 };
775 
776 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
777 	.recover_bus = fsl_i2c_bus_recovery,
778 };
779 
fsl_i2c_probe(struct platform_device * op)780 static int fsl_i2c_probe(struct platform_device *op)
781 {
782 	const struct mpc_i2c_data *data;
783 	struct mpc_i2c *i2c;
784 	struct clk *clk;
785 	int result;
786 	u32 clock;
787 	int err;
788 
789 	i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL);
790 	if (!i2c)
791 		return -ENOMEM;
792 
793 	i2c->dev = &op->dev; /* for debug and error output */
794 
795 	init_waitqueue_head(&i2c->waitq);
796 	spin_lock_init(&i2c->lock);
797 
798 	i2c->base = devm_platform_ioremap_resource(op, 0);
799 	if (IS_ERR(i2c->base))
800 		return PTR_ERR(i2c->base);
801 
802 	i2c->irq = platform_get_irq(op, 0);
803 	if (i2c->irq < 0)
804 		return i2c->irq;
805 
806 	result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr,
807 			IRQF_SHARED, "i2c-mpc", i2c);
808 	if (result < 0) {
809 		dev_err(i2c->dev, "failed to attach interrupt\n");
810 		return result;
811 	}
812 
813 	/*
814 	 * enable clock for the I2C peripheral (non fatal),
815 	 * keep a reference upon successful allocation
816 	 */
817 	clk = devm_clk_get_optional(&op->dev, NULL);
818 	if (IS_ERR(clk))
819 		return PTR_ERR(clk);
820 
821 	err = clk_prepare_enable(clk);
822 	if (err) {
823 		dev_err(&op->dev, "failed to enable clock\n");
824 		return err;
825 	}
826 
827 	i2c->clk_per = clk;
828 
829 	if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
830 		clock = MPC_I2C_CLOCK_PRESERVE;
831 	} else {
832 		result = of_property_read_u32(op->dev.of_node,
833 					      "clock-frequency", &clock);
834 		if (result)
835 			clock = MPC_I2C_CLOCK_LEGACY;
836 	}
837 
838 	data = device_get_match_data(&op->dev);
839 	if (data) {
840 		data->setup(op->dev.of_node, i2c, clock);
841 	} else {
842 		/* Backwards compatibility */
843 		if (of_property_read_bool(op->dev.of_node, "dfsrr"))
844 			mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
845 	}
846 
847 	/*
848 	 * "fsl,timeout" has been marked as deprecated and, to maintain
849 	 * backward compatibility, we will only look for it if
850 	 * "i2c-scl-clk-low-timeout-us" is not present.
851 	 */
852 	result = of_property_read_u32(op->dev.of_node,
853 				      "i2c-scl-clk-low-timeout-us",
854 				      &mpc_ops.timeout);
855 	if (result == -EINVAL)
856 		result = of_property_read_u32(op->dev.of_node,
857 					      "fsl,timeout", &mpc_ops.timeout);
858 
859 	if (!result) {
860 		mpc_ops.timeout *= HZ / 1000000;
861 		if (mpc_ops.timeout < 5)
862 			mpc_ops.timeout = 5;
863 	} else {
864 		mpc_ops.timeout = HZ;
865 	}
866 
867 	dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
868 
869 	if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
870 		i2c->has_errata_A004447 = true;
871 
872 	i2c->adap = mpc_ops;
873 	scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
874 		  "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
875 	i2c->adap.dev.parent = &op->dev;
876 	i2c->adap.nr = op->id;
877 	i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
878 	i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
879 	platform_set_drvdata(op, i2c);
880 	i2c_set_adapdata(&i2c->adap, i2c);
881 
882 	result = i2c_add_numbered_adapter(&i2c->adap);
883 	if (result)
884 		goto fail_add;
885 
886 	return 0;
887 
888  fail_add:
889 	clk_disable_unprepare(i2c->clk_per);
890 
891 	return result;
892 };
893 
fsl_i2c_remove(struct platform_device * op)894 static void fsl_i2c_remove(struct platform_device *op)
895 {
896 	struct mpc_i2c *i2c = platform_get_drvdata(op);
897 
898 	i2c_del_adapter(&i2c->adap);
899 
900 	clk_disable_unprepare(i2c->clk_per);
901 };
902 
mpc_i2c_suspend(struct device * dev)903 static int __maybe_unused mpc_i2c_suspend(struct device *dev)
904 {
905 	struct mpc_i2c *i2c = dev_get_drvdata(dev);
906 
907 	i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
908 	i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
909 
910 	return 0;
911 }
912 
mpc_i2c_resume(struct device * dev)913 static int __maybe_unused mpc_i2c_resume(struct device *dev)
914 {
915 	struct mpc_i2c *i2c = dev_get_drvdata(dev);
916 
917 	writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
918 	writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
919 
920 	return 0;
921 }
922 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
923 
924 static const struct mpc_i2c_data mpc_i2c_data_512x = {
925 	.setup = mpc_i2c_setup_512x,
926 };
927 
928 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
929 	.setup = mpc_i2c_setup_52xx,
930 };
931 
932 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
933 	.setup = mpc_i2c_setup_8xxx,
934 };
935 
936 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
937 	.setup = mpc_i2c_setup_8xxx,
938 };
939 
940 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
941 	.setup = mpc_i2c_setup_8xxx,
942 };
943 
944 static const struct of_device_id mpc_i2c_of_match[] = {
945 	{.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
946 	{.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
947 	{.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
948 	{.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
949 	{.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
950 	{.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
951 	{.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
952 	/* Backward compatibility */
953 	{.compatible = "fsl-i2c", },
954 	{},
955 };
956 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
957 
958 /* Structure for a device driver */
959 static struct platform_driver mpc_i2c_driver = {
960 	.probe		= fsl_i2c_probe,
961 	.remove_new	= fsl_i2c_remove,
962 	.driver = {
963 		.name = DRV_NAME,
964 		.of_match_table = mpc_i2c_of_match,
965 		.pm = &mpc_i2c_pm_ops,
966 	},
967 };
968 
969 module_platform_driver(mpc_i2c_driver);
970 
971 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
972 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
973 		   "MPC824x/83xx/85xx/86xx/512x/52xx processors");
974 MODULE_LICENSE("GPL");
975