xref: /openbmc/linux/sound/soc/codecs/wm8985.c (revision 2fa0213e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * wm8985.c  --  WM8985 / WM8758 ALSA SoC Audio driver
4  *
5  * Copyright 2010 Wolfson Microelectronics plc
6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7  *
8  * WM8758 support:
9  * Copyright: 2016 Barix AG
10  * Author: Petr Kulhavy <petr@barix.com>
11  *
12  * TODO:
13  *  o Add OUT3/OUT4 mixer controls.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/pm.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/spi/spi.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 
33 #include "wm8985.h"
34 
35 #define WM8985_NUM_SUPPLIES 4
36 static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
37 	"DCVDD",
38 	"DBVDD",
39 	"AVDD1",
40 	"AVDD2"
41 };
42 
43 enum wm8985_type {
44 	WM8985,
45 	WM8758,
46 };
47 
48 static const struct reg_default wm8985_reg_defaults[] = {
49 	{ 1,  0x0000 },     /* R1  - Power management 1 */
50 	{ 2,  0x0000 },     /* R2  - Power management 2 */
51 	{ 3,  0x0000 },     /* R3  - Power management 3 */
52 	{ 4,  0x0050 },     /* R4  - Audio Interface */
53 	{ 5,  0x0000 },     /* R5  - Companding control */
54 	{ 6,  0x0140 },     /* R6  - Clock Gen control */
55 	{ 7,  0x0000 },     /* R7  - Additional control */
56 	{ 8,  0x0000 },     /* R8  - GPIO Control */
57 	{ 9,  0x0000 },     /* R9  - Jack Detect Control 1 */
58 	{ 10, 0x0000 },     /* R10 - DAC Control */
59 	{ 11, 0x00FF },     /* R11 - Left DAC digital Vol */
60 	{ 12, 0x00FF },     /* R12 - Right DAC digital vol */
61 	{ 13, 0x0000 },     /* R13 - Jack Detect Control 2 */
62 	{ 14, 0x0100 },     /* R14 - ADC Control */
63 	{ 15, 0x00FF },     /* R15 - Left ADC Digital Vol */
64 	{ 16, 0x00FF },     /* R16 - Right ADC Digital Vol */
65 	{ 18, 0x012C },     /* R18 - EQ1 - low shelf */
66 	{ 19, 0x002C },     /* R19 - EQ2 - peak 1 */
67 	{ 20, 0x002C },     /* R20 - EQ3 - peak 2 */
68 	{ 21, 0x002C },     /* R21 - EQ4 - peak 3 */
69 	{ 22, 0x002C },     /* R22 - EQ5 - high shelf */
70 	{ 24, 0x0032 },     /* R24 - DAC Limiter 1 */
71 	{ 25, 0x0000 },     /* R25 - DAC Limiter 2 */
72 	{ 27, 0x0000 },     /* R27 - Notch Filter 1 */
73 	{ 28, 0x0000 },     /* R28 - Notch Filter 2 */
74 	{ 29, 0x0000 },     /* R29 - Notch Filter 3 */
75 	{ 30, 0x0000 },     /* R30 - Notch Filter 4 */
76 	{ 32, 0x0038 },     /* R32 - ALC control 1 */
77 	{ 33, 0x000B },     /* R33 - ALC control 2 */
78 	{ 34, 0x0032 },     /* R34 - ALC control 3 */
79 	{ 35, 0x0000 },     /* R35 - Noise Gate */
80 	{ 36, 0x0008 },     /* R36 - PLL N */
81 	{ 37, 0x000C },     /* R37 - PLL K 1 */
82 	{ 38, 0x0093 },     /* R38 - PLL K 2 */
83 	{ 39, 0x00E9 },     /* R39 - PLL K 3 */
84 	{ 41, 0x0000 },     /* R41 - 3D control */
85 	{ 42, 0x0000 },     /* R42 - OUT4 to ADC */
86 	{ 43, 0x0000 },     /* R43 - Beep control */
87 	{ 44, 0x0033 },     /* R44 - Input ctrl */
88 	{ 45, 0x0010 },     /* R45 - Left INP PGA gain ctrl */
89 	{ 46, 0x0010 },     /* R46 - Right INP PGA gain ctrl */
90 	{ 47, 0x0100 },     /* R47 - Left ADC BOOST ctrl */
91 	{ 48, 0x0100 },     /* R48 - Right ADC BOOST ctrl */
92 	{ 49, 0x0002 },     /* R49 - Output ctrl */
93 	{ 50, 0x0001 },     /* R50 - Left mixer ctrl */
94 	{ 51, 0x0001 },     /* R51 - Right mixer ctrl */
95 	{ 52, 0x0039 },     /* R52 - LOUT1 (HP) volume ctrl */
96 	{ 53, 0x0039 },     /* R53 - ROUT1 (HP) volume ctrl */
97 	{ 54, 0x0039 },     /* R54 - LOUT2 (SPK) volume ctrl */
98 	{ 55, 0x0039 },     /* R55 - ROUT2 (SPK) volume ctrl */
99 	{ 56, 0x0001 },     /* R56 - OUT3 mixer ctrl */
100 	{ 57, 0x0001 },     /* R57 - OUT4 (MONO) mix ctrl */
101 	{ 60, 0x0004 },     /* R60 - OUTPUT ctrl */
102 	{ 61, 0x0000 },     /* R61 - BIAS CTRL */
103 };
104 
wm8985_writeable(struct device * dev,unsigned int reg)105 static bool wm8985_writeable(struct device *dev, unsigned int reg)
106 {
107 	switch (reg) {
108 	case WM8985_SOFTWARE_RESET:
109 	case WM8985_POWER_MANAGEMENT_1:
110 	case WM8985_POWER_MANAGEMENT_2:
111 	case WM8985_POWER_MANAGEMENT_3:
112 	case WM8985_AUDIO_INTERFACE:
113 	case WM8985_COMPANDING_CONTROL:
114 	case WM8985_CLOCK_GEN_CONTROL:
115 	case WM8985_ADDITIONAL_CONTROL:
116 	case WM8985_GPIO_CONTROL:
117 	case WM8985_JACK_DETECT_CONTROL_1:
118 	case WM8985_DAC_CONTROL:
119 	case WM8985_LEFT_DAC_DIGITAL_VOL:
120 	case WM8985_RIGHT_DAC_DIGITAL_VOL:
121 	case WM8985_JACK_DETECT_CONTROL_2:
122 	case WM8985_ADC_CONTROL:
123 	case WM8985_LEFT_ADC_DIGITAL_VOL:
124 	case WM8985_RIGHT_ADC_DIGITAL_VOL:
125 	case WM8985_EQ1_LOW_SHELF:
126 	case WM8985_EQ2_PEAK_1:
127 	case WM8985_EQ3_PEAK_2:
128 	case WM8985_EQ4_PEAK_3:
129 	case WM8985_EQ5_HIGH_SHELF:
130 	case WM8985_DAC_LIMITER_1:
131 	case WM8985_DAC_LIMITER_2:
132 	case WM8985_NOTCH_FILTER_1:
133 	case WM8985_NOTCH_FILTER_2:
134 	case WM8985_NOTCH_FILTER_3:
135 	case WM8985_NOTCH_FILTER_4:
136 	case WM8985_ALC_CONTROL_1:
137 	case WM8985_ALC_CONTROL_2:
138 	case WM8985_ALC_CONTROL_3:
139 	case WM8985_NOISE_GATE:
140 	case WM8985_PLL_N:
141 	case WM8985_PLL_K_1:
142 	case WM8985_PLL_K_2:
143 	case WM8985_PLL_K_3:
144 	case WM8985_3D_CONTROL:
145 	case WM8985_OUT4_TO_ADC:
146 	case WM8985_BEEP_CONTROL:
147 	case WM8985_INPUT_CTRL:
148 	case WM8985_LEFT_INP_PGA_GAIN_CTRL:
149 	case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
150 	case WM8985_LEFT_ADC_BOOST_CTRL:
151 	case WM8985_RIGHT_ADC_BOOST_CTRL:
152 	case WM8985_OUTPUT_CTRL0:
153 	case WM8985_LEFT_MIXER_CTRL:
154 	case WM8985_RIGHT_MIXER_CTRL:
155 	case WM8985_LOUT1_HP_VOLUME_CTRL:
156 	case WM8985_ROUT1_HP_VOLUME_CTRL:
157 	case WM8985_LOUT2_SPK_VOLUME_CTRL:
158 	case WM8985_ROUT2_SPK_VOLUME_CTRL:
159 	case WM8985_OUT3_MIXER_CTRL:
160 	case WM8985_OUT4_MONO_MIX_CTRL:
161 	case WM8985_OUTPUT_CTRL1:
162 	case WM8985_BIAS_CTRL:
163 		return true;
164 	default:
165 		return false;
166 	}
167 }
168 
169 /*
170  * latch bit 8 of these registers to ensure instant
171  * volume updates
172  */
173 static const int volume_update_regs[] = {
174 	WM8985_LEFT_DAC_DIGITAL_VOL,
175 	WM8985_RIGHT_DAC_DIGITAL_VOL,
176 	WM8985_LEFT_ADC_DIGITAL_VOL,
177 	WM8985_RIGHT_ADC_DIGITAL_VOL,
178 	WM8985_LOUT2_SPK_VOLUME_CTRL,
179 	WM8985_ROUT2_SPK_VOLUME_CTRL,
180 	WM8985_LOUT1_HP_VOLUME_CTRL,
181 	WM8985_ROUT1_HP_VOLUME_CTRL,
182 	WM8985_LEFT_INP_PGA_GAIN_CTRL,
183 	WM8985_RIGHT_INP_PGA_GAIN_CTRL
184 };
185 
186 struct wm8985_priv {
187 	struct regmap *regmap;
188 	struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
189 	enum wm8985_type dev_type;
190 	unsigned int sysclk;
191 	unsigned int bclk;
192 };
193 
194 static const struct {
195 	int div;
196 	int ratio;
197 } fs_ratios[] = {
198 	{ 10, 128 },
199 	{ 15, 192 },
200 	{ 20, 256 },
201 	{ 30, 384 },
202 	{ 40, 512 },
203 	{ 60, 768 },
204 	{ 80, 1024 },
205 	{ 120, 1536 }
206 };
207 
208 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
209 
210 static const int bclk_divs[] = {
211 	1, 2, 4, 8, 16, 32
212 };
213 
214 static int eqmode_get(struct snd_kcontrol *kcontrol,
215 		      struct snd_ctl_elem_value *ucontrol);
216 static int eqmode_put(struct snd_kcontrol *kcontrol,
217 		      struct snd_ctl_elem_value *ucontrol);
218 
219 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
220 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
221 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
222 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
223 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
224 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
225 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
226 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
227 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
228 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
229 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
230 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
231 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
232 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
233 
234 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
235 static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
236 
237 static const char *alc_mode_text[] = { "ALC", "Limiter" };
238 static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
239 
240 static const char *filter_mode_text[] = { "Audio", "Application" };
241 static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
242 			    filter_mode_text);
243 
244 static const char *eq_bw_text[] = { "Narrow", "Wide" };
245 static const char *eqmode_text[] = { "Capture", "Playback" };
246 static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
247 
248 static const char *eq1_cutoff_text[] = {
249 	"80Hz", "105Hz", "135Hz", "175Hz"
250 };
251 static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
252 			    eq1_cutoff_text);
253 static const char *eq2_cutoff_text[] = {
254 	"230Hz", "300Hz", "385Hz", "500Hz"
255 };
256 static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
257 static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
258 static const char *eq3_cutoff_text[] = {
259 	"650Hz", "850Hz", "1.1kHz", "1.4kHz"
260 };
261 static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
262 static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
263 			    eq3_cutoff_text);
264 static const char *eq4_cutoff_text[] = {
265 	"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
266 };
267 static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
268 static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
269 static const char *eq5_cutoff_text[] = {
270 	"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
271 };
272 static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
273 				  eq5_cutoff_text);
274 
275 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
276 static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
277 
278 static const char *depth_3d_text[] = {
279 	"Off",
280 	"6.67%",
281 	"13.3%",
282 	"20%",
283 	"26.7%",
284 	"33.3%",
285 	"40%",
286 	"46.6%",
287 	"53.3%",
288 	"60%",
289 	"66.7%",
290 	"73.3%",
291 	"80%",
292 	"86.7%",
293 	"93.3%",
294 	"100%"
295 };
296 static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
297 
298 static const struct snd_kcontrol_new wm8985_common_snd_controls[] = {
299 	SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
300 		0, 1, 0),
301 
302 	SOC_ENUM("ALC Capture Function", alc_sel),
303 	SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
304 		3, 7, 0, alc_max_tlv),
305 	SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
306 		0, 7, 0, alc_min_tlv),
307 	SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
308 		0, 15, 0, alc_tar_tlv),
309 	SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
310 	SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
311 	SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
312 	SOC_ENUM("ALC Mode", alc_mode),
313 	SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
314 		3, 1, 0),
315 	SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
316 		0, 7, 1),
317 
318 	SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
319 		WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
320 	SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
321 		WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
322 	SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
323 		WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
324 
325 	SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
326 		WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
327 		8, 1, 0, pga_boost_tlv),
328 
329 	SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
330 	SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
331 
332 	SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
333 		WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
334 
335 	SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
336 	SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
337 	SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
338 	SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
339 		4, 7, 1, lim_thresh_tlv),
340 	SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
341 		0, 12, 0, lim_boost_tlv),
342 	SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
343 	SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
344 	SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
345 
346 	SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
347 		WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
348 	SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
349 		WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
350 	SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
351 		WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
352 
353 	SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
354 		WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
355 	SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
356 		WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
357 	SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
358 		WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
359 
360 	SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
361 	SOC_ENUM("High Pass Filter Mode", filter_mode),
362 	SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
363 
364 	SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
365 		WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
366 		bypass_tlv),
367 
368 	SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
369 	SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
370 	SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
371 	SOC_ENUM("EQ2 Bandwidth", eq2_bw),
372 	SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
373 	SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
374 	SOC_ENUM("EQ3 Bandwidth", eq3_bw),
375 	SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
376 	SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
377 	SOC_ENUM("EQ4 Bandwidth", eq4_bw),
378 	SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
379 	SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
380 	SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
381 	SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
382 
383 	SOC_ENUM("3D Depth", depth_3d),
384 };
385 
386 static const struct snd_kcontrol_new wm8985_specific_snd_controls[] = {
387 	SOC_DOUBLE_R_TLV("Aux Bypass Volume",
388 		WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
389 		aux_tlv),
390 
391 	SOC_ENUM("Speaker Mode", speaker_mode)
392 };
393 
394 static const struct snd_kcontrol_new left_out_mixer[] = {
395 	SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
396 	SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
397 
398 	/* --- WM8985 only --- */
399 	SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
400 };
401 
402 static const struct snd_kcontrol_new right_out_mixer[] = {
403 	SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
404 	SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
405 
406 	/* --- WM8985 only --- */
407 	SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
408 };
409 
410 static const struct snd_kcontrol_new left_input_mixer[] = {
411 	SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
412 	SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
413 	SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
414 };
415 
416 static const struct snd_kcontrol_new right_input_mixer[] = {
417 	SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
418 	SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
419 	SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
420 };
421 
422 static const struct snd_kcontrol_new left_boost_mixer[] = {
423 	SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
424 		4, 7, 0, boost_tlv),
425 
426 	/* --- WM8985 only --- */
427 	SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
428 		0, 7, 0, boost_tlv)
429 };
430 
431 static const struct snd_kcontrol_new right_boost_mixer[] = {
432 	SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
433 		4, 7, 0, boost_tlv),
434 
435 	/* --- WM8985 only --- */
436 	SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
437 		0, 7, 0, boost_tlv)
438 };
439 
440 static const struct snd_soc_dapm_widget wm8985_common_dapm_widgets[] = {
441 	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
442 		0, 0),
443 	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
444 		1, 0),
445 	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
446 		0, 0),
447 	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
448 		1, 0),
449 
450 	SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
451 		2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
452 	SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
453 		3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
454 
455 	SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
456 		6, 1, NULL, 0),
457 	SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
458 		6, 1, NULL, 0),
459 
460 	SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
461 		7, 0, NULL, 0),
462 	SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
463 		8, 0, NULL, 0),
464 
465 	SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
466 		5, 0, NULL, 0),
467 	SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
468 		6, 0, NULL, 0),
469 
470 	SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
471 			    NULL, 0),
472 
473 	SND_SOC_DAPM_INPUT("LIN"),
474 	SND_SOC_DAPM_INPUT("LIP"),
475 	SND_SOC_DAPM_INPUT("RIN"),
476 	SND_SOC_DAPM_INPUT("RIP"),
477 	SND_SOC_DAPM_INPUT("L2"),
478 	SND_SOC_DAPM_INPUT("R2"),
479 	SND_SOC_DAPM_OUTPUT("HPL"),
480 	SND_SOC_DAPM_OUTPUT("HPR"),
481 	SND_SOC_DAPM_OUTPUT("SPKL"),
482 	SND_SOC_DAPM_OUTPUT("SPKR")
483 };
484 
485 static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
486 	SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
487 		2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
488 	SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
489 		3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
490 
491 	SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
492 		4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
493 	SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
494 		5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
495 
496 	SND_SOC_DAPM_INPUT("AUXL"),
497 	SND_SOC_DAPM_INPUT("AUXR"),
498 };
499 
500 static const struct snd_soc_dapm_widget wm8758_dapm_widgets[] = {
501 	SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
502 		2, 0, left_out_mixer,
503 		ARRAY_SIZE(left_out_mixer) - 1),
504 	SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
505 		3, 0, right_out_mixer,
506 		ARRAY_SIZE(right_out_mixer) - 1),
507 
508 	SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
509 		4, 0, left_boost_mixer,
510 		ARRAY_SIZE(left_boost_mixer) - 1),
511 	SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
512 		5, 0, right_boost_mixer,
513 		ARRAY_SIZE(right_boost_mixer) - 1),
514 };
515 
516 static const struct snd_soc_dapm_route wm8985_common_dapm_routes[] = {
517 	{ "Right Output Mixer", "PCM Switch", "Right DAC" },
518 	{ "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
519 
520 	{ "Left Output Mixer", "PCM Switch", "Left DAC" },
521 	{ "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
522 
523 	{ "Right Headphone Out", NULL, "Right Output Mixer" },
524 	{ "HPR", NULL, "Right Headphone Out" },
525 
526 	{ "Left Headphone Out", NULL, "Left Output Mixer" },
527 	{ "HPL", NULL, "Left Headphone Out" },
528 
529 	{ "Right Speaker Out", NULL, "Right Output Mixer" },
530 	{ "SPKR", NULL, "Right Speaker Out" },
531 
532 	{ "Left Speaker Out", NULL, "Left Output Mixer" },
533 	{ "SPKL", NULL, "Left Speaker Out" },
534 
535 	{ "Right ADC", NULL, "Right Boost Mixer" },
536 
537 	{ "Right Boost Mixer", NULL, "Right Capture PGA" },
538 	{ "Right Boost Mixer", "R2 Volume", "R2" },
539 
540 	{ "Left ADC", NULL, "Left Boost Mixer" },
541 
542 	{ "Left Boost Mixer", NULL, "Left Capture PGA" },
543 	{ "Left Boost Mixer", "L2 Volume", "L2" },
544 
545 	{ "Right Capture PGA", NULL, "Right Input Mixer" },
546 	{ "Left Capture PGA", NULL, "Left Input Mixer" },
547 
548 	{ "Right Input Mixer", "R2 Switch", "R2" },
549 	{ "Right Input Mixer", "MicN Switch", "RIN" },
550 	{ "Right Input Mixer", "MicP Switch", "RIP" },
551 
552 	{ "Left Input Mixer", "L2 Switch", "L2" },
553 	{ "Left Input Mixer", "MicN Switch", "LIN" },
554 	{ "Left Input Mixer", "MicP Switch", "LIP" },
555 };
556 static const struct snd_soc_dapm_route wm8985_aux_dapm_routes[] = {
557 	{ "Right Output Mixer", "Aux Switch", "AUXR" },
558 	{ "Left Output Mixer", "Aux Switch", "AUXL" },
559 
560 	{ "Right Boost Mixer", "AUXR Volume", "AUXR" },
561 	{ "Left Boost Mixer", "AUXL Volume", "AUXL" },
562 };
563 
wm8985_add_widgets(struct snd_soc_component * component)564 static int wm8985_add_widgets(struct snd_soc_component *component)
565 {
566 	struct wm8985_priv *wm8985 = snd_soc_component_get_drvdata(component);
567 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
568 
569 	switch (wm8985->dev_type) {
570 	case WM8758:
571 		snd_soc_dapm_new_controls(dapm, wm8758_dapm_widgets,
572 					  ARRAY_SIZE(wm8758_dapm_widgets));
573 		break;
574 
575 	case WM8985:
576 		snd_soc_add_component_controls(component, wm8985_specific_snd_controls,
577 			ARRAY_SIZE(wm8985_specific_snd_controls));
578 
579 		snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
580 			ARRAY_SIZE(wm8985_dapm_widgets));
581 		snd_soc_dapm_add_routes(dapm, wm8985_aux_dapm_routes,
582 			ARRAY_SIZE(wm8985_aux_dapm_routes));
583 		break;
584 	}
585 
586 	return 0;
587 }
588 
eqmode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)589 static int eqmode_get(struct snd_kcontrol *kcontrol,
590 		      struct snd_ctl_elem_value *ucontrol)
591 {
592 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
593 	unsigned int reg;
594 
595 	reg = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
596 	if (reg & WM8985_EQ3DMODE)
597 		ucontrol->value.enumerated.item[0] = 1;
598 	else
599 		ucontrol->value.enumerated.item[0] = 0;
600 
601 	return 0;
602 }
603 
eqmode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)604 static int eqmode_put(struct snd_kcontrol *kcontrol,
605 		      struct snd_ctl_elem_value *ucontrol)
606 {
607 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
608 	unsigned int regpwr2, regpwr3;
609 	unsigned int reg_eq;
610 
611 	if (ucontrol->value.enumerated.item[0] != 0
612 			&& ucontrol->value.enumerated.item[0] != 1)
613 		return -EINVAL;
614 
615 	reg_eq = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
616 	switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
617 	case 0:
618 		if (!ucontrol->value.enumerated.item[0])
619 			return 0;
620 		break;
621 	case 1:
622 		if (ucontrol->value.enumerated.item[0])
623 			return 0;
624 		break;
625 	}
626 
627 	regpwr2 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_2);
628 	regpwr3 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_3);
629 	/* disable the DACs and ADCs */
630 	snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_2,
631 			    WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
632 	snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_3,
633 			    WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
634 	snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
635 			    WM8985_M128ENB_MASK, WM8985_M128ENB);
636 	/* set the desired eqmode */
637 	snd_soc_component_update_bits(component, WM8985_EQ1_LOW_SHELF,
638 			    WM8985_EQ3DMODE_MASK,
639 			    ucontrol->value.enumerated.item[0]
640 			    << WM8985_EQ3DMODE_SHIFT);
641 	/* restore DAC/ADC configuration */
642 	snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, regpwr2);
643 	snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, regpwr3);
644 	return 0;
645 }
646 
wm8985_reset(struct snd_soc_component * component)647 static int wm8985_reset(struct snd_soc_component *component)
648 {
649 	return snd_soc_component_write(component, WM8985_SOFTWARE_RESET, 0x0);
650 }
651 
wm8985_dac_mute(struct snd_soc_dai * dai,int mute,int direction)652 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
653 {
654 	struct snd_soc_component *component = dai->component;
655 
656 	return snd_soc_component_update_bits(component, WM8985_DAC_CONTROL,
657 				   WM8985_SOFTMUTE_MASK,
658 				   !!mute << WM8985_SOFTMUTE_SHIFT);
659 }
660 
wm8985_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)661 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
662 {
663 	struct snd_soc_component *component;
664 	u16 format, master, bcp, lrp;
665 
666 	component = dai->component;
667 
668 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
669 	case SND_SOC_DAIFMT_I2S:
670 		format = 0x2;
671 		break;
672 	case SND_SOC_DAIFMT_RIGHT_J:
673 		format = 0x0;
674 		break;
675 	case SND_SOC_DAIFMT_LEFT_J:
676 		format = 0x1;
677 		break;
678 	case SND_SOC_DAIFMT_DSP_A:
679 	case SND_SOC_DAIFMT_DSP_B:
680 		format = 0x3;
681 		break;
682 	default:
683 		dev_err(dai->dev, "Unknown dai format\n");
684 		return -EINVAL;
685 	}
686 
687 	snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
688 			    WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
689 
690 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
691 	case SND_SOC_DAIFMT_CBM_CFM:
692 		master = 1;
693 		break;
694 	case SND_SOC_DAIFMT_CBS_CFS:
695 		master = 0;
696 		break;
697 	default:
698 		dev_err(dai->dev, "Unknown master/slave configuration\n");
699 		return -EINVAL;
700 	}
701 
702 	snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
703 			    WM8985_MS_MASK, master << WM8985_MS_SHIFT);
704 
705 	/* frame inversion is not valid for dsp modes */
706 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
707 	case SND_SOC_DAIFMT_DSP_A:
708 	case SND_SOC_DAIFMT_DSP_B:
709 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
710 		case SND_SOC_DAIFMT_IB_IF:
711 		case SND_SOC_DAIFMT_NB_IF:
712 			return -EINVAL;
713 		default:
714 			break;
715 		}
716 		break;
717 	default:
718 		break;
719 	}
720 
721 	bcp = lrp = 0;
722 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
723 	case SND_SOC_DAIFMT_NB_NF:
724 		break;
725 	case SND_SOC_DAIFMT_IB_IF:
726 		bcp = lrp = 1;
727 		break;
728 	case SND_SOC_DAIFMT_IB_NF:
729 		bcp = 1;
730 		break;
731 	case SND_SOC_DAIFMT_NB_IF:
732 		lrp = 1;
733 		break;
734 	default:
735 		dev_err(dai->dev, "Unknown polarity configuration\n");
736 		return -EINVAL;
737 	}
738 
739 	snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
740 			    WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
741 	snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
742 			    WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
743 	return 0;
744 }
745 
wm8985_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)746 static int wm8985_hw_params(struct snd_pcm_substream *substream,
747 			    struct snd_pcm_hw_params *params,
748 			    struct snd_soc_dai *dai)
749 {
750 	int i;
751 	struct snd_soc_component *component;
752 	struct wm8985_priv *wm8985;
753 	u16 blen, srate_idx;
754 	unsigned int tmp;
755 	int srate_best;
756 
757 	component = dai->component;
758 	wm8985 = snd_soc_component_get_drvdata(component);
759 
760 	wm8985->bclk = snd_soc_params_to_bclk(params);
761 	if ((int)wm8985->bclk < 0)
762 		return wm8985->bclk;
763 
764 	switch (params_width(params)) {
765 	case 16:
766 		blen = 0x0;
767 		break;
768 	case 20:
769 		blen = 0x1;
770 		break;
771 	case 24:
772 		blen = 0x2;
773 		break;
774 	case 32:
775 		blen = 0x3;
776 		break;
777 	default:
778 		dev_err(dai->dev, "Unsupported word length %u\n",
779 			params_width(params));
780 		return -EINVAL;
781 	}
782 
783 	snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
784 			    WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
785 
786 	/*
787 	 * match to the nearest possible sample rate and rely
788 	 * on the array index to configure the SR register
789 	 */
790 	srate_idx = 0;
791 	srate_best = abs(srates[0] - params_rate(params));
792 	for (i = 1; i < ARRAY_SIZE(srates); ++i) {
793 		if (abs(srates[i] - params_rate(params)) >= srate_best)
794 			continue;
795 		srate_idx = i;
796 		srate_best = abs(srates[i] - params_rate(params));
797 	}
798 
799 	dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
800 	snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
801 			    WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
802 
803 	dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
804 	dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
805 
806 	for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
807 		if (wm8985->sysclk / params_rate(params)
808 				== fs_ratios[i].ratio)
809 			break;
810 	}
811 
812 	if (i == ARRAY_SIZE(fs_ratios)) {
813 		dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
814 			wm8985->sysclk, params_rate(params));
815 		return -EINVAL;
816 	}
817 
818 	dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
819 	snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
820 			    WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
821 
822 	/* select the appropriate bclk divider */
823 	tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
824 	for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
825 		if (wm8985->bclk == tmp / bclk_divs[i])
826 			break;
827 	}
828 
829 	if (i == ARRAY_SIZE(bclk_divs)) {
830 		dev_err(dai->dev, "No matching BCLK divider found\n");
831 		return -EINVAL;
832 	}
833 
834 	dev_dbg(dai->dev, "BCLK div = %d\n", i);
835 	snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
836 			    WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
837 	return 0;
838 }
839 
840 struct pll_div {
841 	u32 div2:1;
842 	u32 n:4;
843 	u32 k:24;
844 };
845 
846 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
pll_factors(struct pll_div * pll_div,unsigned int target,unsigned int source)847 static int pll_factors(struct pll_div *pll_div, unsigned int target,
848 		       unsigned int source)
849 {
850 	u64 Kpart;
851 	unsigned long int K, Ndiv, Nmod;
852 
853 	pll_div->div2 = 0;
854 	Ndiv = target / source;
855 	if (Ndiv < 6) {
856 		source >>= 1;
857 		pll_div->div2 = 1;
858 		Ndiv = target / source;
859 	}
860 
861 	if (Ndiv < 6 || Ndiv > 12) {
862 		printk(KERN_ERR "%s: WM8985 N value is not within"
863 		       " the recommended range: %lu\n", __func__, Ndiv);
864 		return -EINVAL;
865 	}
866 	pll_div->n = Ndiv;
867 
868 	Nmod = target % source;
869 	Kpart = FIXED_PLL_SIZE * (u64)Nmod;
870 
871 	do_div(Kpart, source);
872 
873 	K = Kpart & 0xffffffff;
874 	if ((K % 10) >= 5)
875 		K += 5;
876 	K /= 10;
877 	pll_div->k = K;
878 
879 	return 0;
880 }
881 
wm8985_set_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)882 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
883 			  int source, unsigned int freq_in,
884 			  unsigned int freq_out)
885 {
886 	int ret;
887 	struct snd_soc_component *component;
888 	struct pll_div pll_div;
889 
890 	component = dai->component;
891 	if (!freq_in || !freq_out) {
892 		/* disable the PLL */
893 		snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
894 				    WM8985_PLLEN_MASK, 0);
895 	} else {
896 		ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
897 		if (ret)
898 			return ret;
899 
900 		/* set PLLN and PRESCALE */
901 		snd_soc_component_write(component, WM8985_PLL_N,
902 			      (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
903 			      | pll_div.n);
904 		/* set PLLK */
905 		snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff);
906 		snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
907 		snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18));
908 		/* set the source of the clock to be the PLL */
909 		snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
910 				    WM8985_CLKSEL_MASK, WM8985_CLKSEL);
911 		/* enable the PLL */
912 		snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
913 				    WM8985_PLLEN_MASK, WM8985_PLLEN);
914 	}
915 	return 0;
916 }
917 
wm8985_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)918 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
919 			     int clk_id, unsigned int freq, int dir)
920 {
921 	struct snd_soc_component *component;
922 	struct wm8985_priv *wm8985;
923 
924 	component = dai->component;
925 	wm8985 = snd_soc_component_get_drvdata(component);
926 
927 	switch (clk_id) {
928 	case WM8985_CLKSRC_MCLK:
929 		snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
930 				    WM8985_CLKSEL_MASK, 0);
931 		snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
932 				    WM8985_PLLEN_MASK, 0);
933 		break;
934 	case WM8985_CLKSRC_PLL:
935 		snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
936 				    WM8985_CLKSEL_MASK, WM8985_CLKSEL);
937 		break;
938 	default:
939 		dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
940 		return -EINVAL;
941 	}
942 
943 	wm8985->sysclk = freq;
944 	return 0;
945 }
946 
wm8985_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)947 static int wm8985_set_bias_level(struct snd_soc_component *component,
948 				 enum snd_soc_bias_level level)
949 {
950 	int ret;
951 	struct wm8985_priv *wm8985;
952 
953 	wm8985 = snd_soc_component_get_drvdata(component);
954 	switch (level) {
955 	case SND_SOC_BIAS_ON:
956 	case SND_SOC_BIAS_PREPARE:
957 		/* VMID at 75k */
958 		snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
959 				    WM8985_VMIDSEL_MASK,
960 				    1 << WM8985_VMIDSEL_SHIFT);
961 		break;
962 	case SND_SOC_BIAS_STANDBY:
963 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
964 			ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
965 						    wm8985->supplies);
966 			if (ret) {
967 				dev_err(component->dev,
968 					"Failed to enable supplies: %d\n",
969 					ret);
970 				return ret;
971 			}
972 
973 			regcache_sync(wm8985->regmap);
974 
975 			/* enable anti-pop features */
976 			snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
977 					    WM8985_POBCTRL_MASK,
978 					    WM8985_POBCTRL);
979 			/* enable thermal shutdown */
980 			snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
981 					    WM8985_TSDEN_MASK, WM8985_TSDEN);
982 			snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
983 					    WM8985_TSOPCTRL_MASK,
984 					    WM8985_TSOPCTRL);
985 			/* enable BIASEN */
986 			snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
987 					    WM8985_BIASEN_MASK, WM8985_BIASEN);
988 			/* VMID at 75k */
989 			snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
990 					    WM8985_VMIDSEL_MASK,
991 					    1 << WM8985_VMIDSEL_SHIFT);
992 			msleep(500);
993 			/* disable anti-pop features */
994 			snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
995 					    WM8985_POBCTRL_MASK, 0);
996 		}
997 		/* VMID at 300k */
998 		snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
999 				    WM8985_VMIDSEL_MASK,
1000 				    2 << WM8985_VMIDSEL_SHIFT);
1001 		break;
1002 	case SND_SOC_BIAS_OFF:
1003 		/* disable thermal shutdown */
1004 		snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
1005 				    WM8985_TSOPCTRL_MASK, 0);
1006 		snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
1007 				    WM8985_TSDEN_MASK, 0);
1008 		/* disable VMIDSEL and BIASEN */
1009 		snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
1010 				    WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
1011 				    0);
1012 		snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_1, 0);
1013 		snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, 0);
1014 		snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, 0);
1015 
1016 		regcache_mark_dirty(wm8985->regmap);
1017 
1018 		regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
1019 				       wm8985->supplies);
1020 		break;
1021 	}
1022 
1023 	return 0;
1024 }
1025 
wm8985_probe(struct snd_soc_component * component)1026 static int wm8985_probe(struct snd_soc_component *component)
1027 {
1028 	size_t i;
1029 	struct wm8985_priv *wm8985;
1030 	int ret;
1031 
1032 	wm8985 = snd_soc_component_get_drvdata(component);
1033 
1034 	for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
1035 		wm8985->supplies[i].supply = wm8985_supply_names[i];
1036 
1037 	ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8985->supplies),
1038 				 wm8985->supplies);
1039 	if (ret) {
1040 		dev_err(component->dev, "Failed to request supplies: %d\n", ret);
1041 		return ret;
1042 	}
1043 
1044 	ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
1045 				    wm8985->supplies);
1046 	if (ret) {
1047 		dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
1048 		return ret;
1049 	}
1050 
1051 	ret = wm8985_reset(component);
1052 	if (ret < 0) {
1053 		dev_err(component->dev, "Failed to issue reset: %d\n", ret);
1054 		goto err_reg_enable;
1055 	}
1056 
1057 	/* latch volume update bits */
1058 	for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
1059 		snd_soc_component_update_bits(component, volume_update_regs[i],
1060 				    0x100, 0x100);
1061 	/* enable BIASCUT */
1062 	snd_soc_component_update_bits(component, WM8985_BIAS_CTRL, WM8985_BIASCUT,
1063 			    WM8985_BIASCUT);
1064 
1065 	wm8985_add_widgets(component);
1066 
1067 	return 0;
1068 
1069 err_reg_enable:
1070 	regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1071 	return ret;
1072 }
1073 
1074 static const struct snd_soc_dai_ops wm8985_dai_ops = {
1075 	.mute_stream = wm8985_dac_mute,
1076 	.hw_params = wm8985_hw_params,
1077 	.set_fmt = wm8985_set_fmt,
1078 	.set_sysclk = wm8985_set_sysclk,
1079 	.set_pll = wm8985_set_pll,
1080 	.no_capture_mute = 1,
1081 };
1082 
1083 #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1084 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1085 
1086 static struct snd_soc_dai_driver wm8985_dai = {
1087 	.name = "wm8985-hifi",
1088 	.playback = {
1089 		.stream_name = "Playback",
1090 		.channels_min = 2,
1091 		.channels_max = 2,
1092 		.rates = SNDRV_PCM_RATE_8000_48000,
1093 		.formats = WM8985_FORMATS,
1094 	},
1095 	.capture = {
1096 		.stream_name = "Capture",
1097 		.channels_min = 2,
1098 		.channels_max = 2,
1099 		.rates = SNDRV_PCM_RATE_8000_48000,
1100 		.formats = WM8985_FORMATS,
1101 	},
1102 	.ops = &wm8985_dai_ops,
1103 	.symmetric_rate = 1
1104 };
1105 
1106 static const struct snd_soc_component_driver soc_component_dev_wm8985 = {
1107 	.probe			= wm8985_probe,
1108 	.set_bias_level		= wm8985_set_bias_level,
1109 	.controls		= wm8985_common_snd_controls,
1110 	.num_controls		= ARRAY_SIZE(wm8985_common_snd_controls),
1111 	.dapm_widgets		= wm8985_common_dapm_widgets,
1112 	.num_dapm_widgets	= ARRAY_SIZE(wm8985_common_dapm_widgets),
1113 	.dapm_routes		= wm8985_common_dapm_routes,
1114 	.num_dapm_routes	= ARRAY_SIZE(wm8985_common_dapm_routes),
1115 	.suspend_bias_off	= 1,
1116 	.idle_bias_on		= 1,
1117 	.use_pmdown_time	= 1,
1118 	.endianness		= 1,
1119 };
1120 
1121 static const struct regmap_config wm8985_regmap = {
1122 	.reg_bits = 7,
1123 	.val_bits = 9,
1124 
1125 	.max_register = WM8985_MAX_REGISTER,
1126 	.writeable_reg = wm8985_writeable,
1127 
1128 	.cache_type = REGCACHE_MAPLE,
1129 	.reg_defaults = wm8985_reg_defaults,
1130 	.num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
1131 };
1132 
1133 #if defined(CONFIG_SPI_MASTER)
wm8985_spi_probe(struct spi_device * spi)1134 static int wm8985_spi_probe(struct spi_device *spi)
1135 {
1136 	struct wm8985_priv *wm8985;
1137 	int ret;
1138 
1139 	wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
1140 	if (!wm8985)
1141 		return -ENOMEM;
1142 
1143 	spi_set_drvdata(spi, wm8985);
1144 
1145 	wm8985->dev_type = WM8985;
1146 
1147 	wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
1148 	if (IS_ERR(wm8985->regmap)) {
1149 		ret = PTR_ERR(wm8985->regmap);
1150 		dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1151 			ret);
1152 		return ret;
1153 	}
1154 
1155 	ret = devm_snd_soc_register_component(&spi->dev,
1156 				     &soc_component_dev_wm8985, &wm8985_dai, 1);
1157 	return ret;
1158 }
1159 
1160 static struct spi_driver wm8985_spi_driver = {
1161 	.driver = {
1162 		.name = "wm8985",
1163 	},
1164 	.probe = wm8985_spi_probe,
1165 };
1166 #endif
1167 
1168 #if IS_ENABLED(CONFIG_I2C)
1169 static const struct i2c_device_id wm8985_i2c_id[];
1170 
wm8985_i2c_probe(struct i2c_client * i2c)1171 static int wm8985_i2c_probe(struct i2c_client *i2c)
1172 {
1173 	struct wm8985_priv *wm8985;
1174 	const struct i2c_device_id *id = i2c_match_id(wm8985_i2c_id, i2c);
1175 	int ret;
1176 
1177 	wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
1178 	if (!wm8985)
1179 		return -ENOMEM;
1180 
1181 	i2c_set_clientdata(i2c, wm8985);
1182 
1183 	wm8985->dev_type = id->driver_data;
1184 
1185 	wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
1186 	if (IS_ERR(wm8985->regmap)) {
1187 		ret = PTR_ERR(wm8985->regmap);
1188 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1189 			ret);
1190 		return ret;
1191 	}
1192 
1193 	ret = devm_snd_soc_register_component(&i2c->dev,
1194 				     &soc_component_dev_wm8985, &wm8985_dai, 1);
1195 	return ret;
1196 }
1197 
1198 static const struct i2c_device_id wm8985_i2c_id[] = {
1199 	{ "wm8985", WM8985 },
1200 	{ "wm8758", WM8758 },
1201 	{ }
1202 };
1203 MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1204 
1205 static struct i2c_driver wm8985_i2c_driver = {
1206 	.driver = {
1207 		.name = "wm8985",
1208 	},
1209 	.probe = wm8985_i2c_probe,
1210 	.id_table = wm8985_i2c_id
1211 };
1212 #endif
1213 
wm8985_modinit(void)1214 static int __init wm8985_modinit(void)
1215 {
1216 	int ret = 0;
1217 
1218 #if IS_ENABLED(CONFIG_I2C)
1219 	ret = i2c_add_driver(&wm8985_i2c_driver);
1220 	if (ret) {
1221 		printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1222 		       ret);
1223 	}
1224 #endif
1225 #if defined(CONFIG_SPI_MASTER)
1226 	ret = spi_register_driver(&wm8985_spi_driver);
1227 	if (ret != 0) {
1228 		printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1229 		       ret);
1230 	}
1231 #endif
1232 	return ret;
1233 }
1234 module_init(wm8985_modinit);
1235 
wm8985_exit(void)1236 static void __exit wm8985_exit(void)
1237 {
1238 #if IS_ENABLED(CONFIG_I2C)
1239 	i2c_del_driver(&wm8985_i2c_driver);
1240 #endif
1241 #if defined(CONFIG_SPI_MASTER)
1242 	spi_unregister_driver(&wm8985_spi_driver);
1243 #endif
1244 }
1245 module_exit(wm8985_exit);
1246 
1247 MODULE_DESCRIPTION("ASoC WM8985 / WM8758 driver");
1248 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1249 MODULE_LICENSE("GPL");
1250