1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
5 */
6
7 #ifndef __DPU_ENCODER_PHYS_H__
8 #define __DPU_ENCODER_PHYS_H__
9
10 #include <drm/drm_writeback.h>
11 #include <linux/jiffies.h>
12
13 #include "dpu_kms.h"
14 #include "dpu_hw_intf.h"
15 #include "dpu_hw_wb.h"
16 #include "dpu_hw_pingpong.h"
17 #include "dpu_hw_ctl.h"
18 #include "dpu_hw_top.h"
19 #include "dpu_encoder.h"
20 #include "dpu_crtc.h"
21
22 #define DPU_ENCODER_NAME_MAX 16
23
24 /* wait for at most 2 vsync for lowest refresh rate (24hz) */
25 #define KICKOFF_TIMEOUT_MS 84
26 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
27
28 /**
29 * enum dpu_enc_split_role - Role this physical encoder will play in a
30 * split-panel configuration, where one panel is master, and others slaves.
31 * Masters have extra responsibilities, like managing the VBLANK IRQ.
32 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
33 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
34 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
35 */
36 enum dpu_enc_split_role {
37 ENC_ROLE_SOLO,
38 ENC_ROLE_MASTER,
39 ENC_ROLE_SLAVE,
40 };
41
42 /**
43 * enum dpu_enc_enable_state - current enabled state of the physical encoder
44 * @DPU_ENC_DISABLING: Encoder transitioning to disable state
45 * Events bounding transition are encoder type specific
46 * @DPU_ENC_DISABLED: Encoder is disabled
47 * @DPU_ENC_ENABLING: Encoder transitioning to enabled
48 * Events bounding transition are encoder type specific
49 * @DPU_ENC_ENABLED: Encoder is enabled
50 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset
51 * to recover from a previous error
52 */
53 enum dpu_enc_enable_state {
54 DPU_ENC_DISABLING,
55 DPU_ENC_DISABLED,
56 DPU_ENC_ENABLING,
57 DPU_ENC_ENABLED,
58 DPU_ENC_ERR_NEEDS_HW_RESET
59 };
60
61 struct dpu_encoder_phys;
62
63 /**
64 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
65 * the containing virtual encoder.
66 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence
67 * @is_master: Whether this phys_enc is the current master
68 * encoder. Can be switched at enable time. Based
69 * on split_role and current mode (CMD/VID).
70 * @atomic_mode_set: DRM Call. Set a DRM mode.
71 * This likely caches the mode, for use at enable.
72 * @enable: DRM Call. Enable a DRM mode.
73 * @disable: DRM Call. Disable mode.
74 * @atomic_check: DRM Call. Atomic check new DRM state.
75 * @destroy: DRM Call. Destroy and release resources.
76 * @control_vblank_irq Register/Deregister for VBLANK IRQ
77 * @wait_for_commit_done: Wait for hardware to have flushed the
78 * current pending frames to hardware
79 * @wait_for_tx_complete: Wait for hardware to transfer the pixels
80 * to the panel
81 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use
82 * @prepare_for_kickoff: Do any work necessary prior to a kickoff
83 * For CMD encoder, may wait for previous tx done
84 * @handle_post_kickoff: Do any work necessary post-kickoff work
85 * @trigger_start: Process start event on physical encoder
86 * @needs_single_flush: Whether encoder slaves need to be flushed
87 * @irq_control: Handler to enable/disable all the encoder IRQs
88 * @prepare_idle_pc: phys encoder can update the vsync_enable status
89 * on idle power collapse prepare
90 * @restore: Restore all the encoder configs.
91 * @get_line_count: Obtain current vertical line count
92 */
93
94 struct dpu_encoder_phys_ops {
95 void (*prepare_commit)(struct dpu_encoder_phys *encoder);
96 bool (*is_master)(struct dpu_encoder_phys *encoder);
97 void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
98 struct drm_crtc_state *crtc_state,
99 struct drm_connector_state *conn_state);
100 void (*enable)(struct dpu_encoder_phys *encoder);
101 void (*disable)(struct dpu_encoder_phys *encoder);
102 int (*atomic_check)(struct dpu_encoder_phys *encoder,
103 struct drm_crtc_state *crtc_state,
104 struct drm_connector_state *conn_state);
105 void (*destroy)(struct dpu_encoder_phys *encoder);
106 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
107 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
108 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
109 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
110 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
111 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
112 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
113 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
114 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
115 void (*restore)(struct dpu_encoder_phys *phys);
116 int (*get_line_count)(struct dpu_encoder_phys *phys);
117 int (*get_frame_count)(struct dpu_encoder_phys *phys);
118 void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
119 struct drm_writeback_job *job);
120 void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
121 struct drm_writeback_job *job);
122 bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
123 };
124
125 /**
126 * enum dpu_intr_idx - dpu encoder interrupt index
127 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel
128 * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
129 * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
130 * @INTR_IDX_RDPTR: Readpointer done interrupt for cmd mode panel
131 * @INTR_IDX_WB_DONE: Writeback done interrupt for virtual connector
132 */
133 enum dpu_intr_idx {
134 INTR_IDX_VSYNC,
135 INTR_IDX_PINGPONG,
136 INTR_IDX_UNDERRUN,
137 INTR_IDX_CTL_START,
138 INTR_IDX_RDPTR,
139 INTR_IDX_WB_DONE,
140 INTR_IDX_MAX,
141 };
142
143 /**
144 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
145 * tied to a specific panel / sub-panel. Abstract type, sub-classed by
146 * phys_vid or phys_cmd for video mode or command mode encs respectively.
147 * @parent: Pointer to the containing virtual encoder
148 * @ops: Operations exposed to the virtual encoder
149 * @parent_ops: Callbacks exposed by the parent to the phys_enc
150 * @hw_mdptop: Hardware interface to the top registers
151 * @hw_ctl: Hardware interface to the ctl registers
152 * @hw_pp: Hardware interface to the ping pong registers
153 * @hw_intf: Hardware interface to the intf registers
154 * @hw_wb: Hardware interface to the wb registers
155 * @dpu_kms: Pointer to the dpu_kms top level
156 * @cached_mode: DRM mode cached at mode_set time, acted on in enable
157 * @enabled: Whether the encoder has enabled and running a mode
158 * @split_role: Role to play in a split-panel configuration
159 * @intf_mode: Interface mode
160 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
161 * @enable_state: Enable state tracking
162 * @vblank_refcount: Reference count of vblank request
163 * @vsync_cnt: Vsync count for the physical encoder
164 * @underrun_cnt: Underrun count for the physical encoder
165 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs
166 * vs. the number of done/vblank irqs. Should hover
167 * between 0-2 Incremented when a new kickoff is
168 * scheduled. Decremented in irq handler
169 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start
170 * pending.
171 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes
172 * @irq: IRQ indices
173 * @has_intf_te: Interface TE configuration support
174 */
175 struct dpu_encoder_phys {
176 struct drm_encoder *parent;
177 struct dpu_encoder_phys_ops ops;
178 struct dpu_hw_mdp *hw_mdptop;
179 struct dpu_hw_ctl *hw_ctl;
180 struct dpu_hw_pingpong *hw_pp;
181 struct dpu_hw_intf *hw_intf;
182 struct dpu_hw_wb *hw_wb;
183 struct dpu_kms *dpu_kms;
184 struct drm_display_mode cached_mode;
185 enum dpu_enc_split_role split_role;
186 enum dpu_intf_mode intf_mode;
187 spinlock_t *enc_spinlock;
188 enum dpu_enc_enable_state enable_state;
189 atomic_t vblank_refcount;
190 atomic_t vsync_cnt;
191 atomic_t underrun_cnt;
192 atomic_t pending_ctlstart_cnt;
193 atomic_t pending_kickoff_cnt;
194 wait_queue_head_t pending_kickoff_wq;
195 int irq[INTR_IDX_MAX];
196 bool has_intf_te;
197 };
198
dpu_encoder_phys_inc_pending(struct dpu_encoder_phys * phys)199 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
200 {
201 atomic_inc_return(&phys->pending_ctlstart_cnt);
202 return atomic_inc_return(&phys->pending_kickoff_cnt);
203 }
204
205 /**
206 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
207 * mode specific operations
208 * @base: Baseclass physical encoder structure
209 * @wbirq_refcount: Reference count of writeback interrupt
210 * @wb_done_timeout_cnt: number of wb done irq timeout errors
211 * @wb_cfg: writeback block config to store fb related details
212 * @wb_conn: backpointer to writeback connector
213 * @wb_job: backpointer to current writeback job
214 * @dest: dpu buffer layout for current writeback output buffer
215 */
216 struct dpu_encoder_phys_wb {
217 struct dpu_encoder_phys base;
218 atomic_t wbirq_refcount;
219 int wb_done_timeout_cnt;
220 struct dpu_hw_wb_cfg wb_cfg;
221 struct drm_writeback_connector *wb_conn;
222 struct drm_writeback_job *wb_job;
223 struct dpu_hw_fmt_layout dest;
224 };
225
226 /**
227 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
228 * mode specific operations
229 * @base: Baseclass physical encoder structure
230 * @intf_idx: Intf Block index used by this phys encoder
231 * @stream_sel: Stream selection for multi-stream interfaces
232 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt
233 * after ctl_start instead of before next frame kickoff
234 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
235 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
236 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
237 */
238 struct dpu_encoder_phys_cmd {
239 struct dpu_encoder_phys base;
240 int stream_sel;
241 bool serialize_wait4pp;
242 int pp_timeout_report_cnt;
243 atomic_t pending_vblank_cnt;
244 wait_queue_head_t pending_vblank_wq;
245 };
246
247 /**
248 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
249 * @dpu_kms: Pointer to the dpu_kms top level
250 * @parent: Pointer to the containing virtual encoder
251 * @parent_ops: Callbacks exposed by the parent to the phys_enc
252 * @split_role: Role to play in a split-panel configuration
253 * @hw_intf: Hardware interface to the intf registers
254 * @hw_wb: Hardware interface to the wb registers
255 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
256 */
257 struct dpu_enc_phys_init_params {
258 struct dpu_kms *dpu_kms;
259 struct drm_encoder *parent;
260 enum dpu_enc_split_role split_role;
261 struct dpu_hw_intf *hw_intf;
262 struct dpu_hw_wb *hw_wb;
263 spinlock_t *enc_spinlock;
264 };
265
266 /**
267 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
268 * @wq: wait queue structure
269 * @atomic_cnt: wait until atomic_cnt equals zero
270 * @timeout_ms: timeout value in milliseconds
271 */
272 struct dpu_encoder_wait_info {
273 wait_queue_head_t *wq;
274 atomic_t *atomic_cnt;
275 s64 timeout_ms;
276 };
277
278 /**
279 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
280 * @p: Pointer to init params structure
281 * Return: Error code or newly allocated encoder
282 */
283 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
284 struct dpu_enc_phys_init_params *p);
285
286 /**
287 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
288 * @dev: Corresponding device for devres management
289 * @p: Pointer to init params structure
290 * Return: Error code or newly allocated encoder
291 */
292 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev,
293 struct dpu_enc_phys_init_params *p);
294
295 /**
296 * dpu_encoder_phys_wb_init - initialize writeback encoder
297 * @dev: Corresponding device for devres management
298 * @init: Pointer to init info structure with initialization params
299 */
300 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
301 struct dpu_enc_phys_init_params *p);
302
303 /**
304 * dpu_encoder_helper_trigger_start - control start helper function
305 * This helper function may be optionally specified by physical
306 * encoders if they require ctl_start triggering.
307 * @phys_enc: Pointer to physical encoder structure
308 */
309 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
310
dpu_encoder_helper_get_3d_blend_mode(struct dpu_encoder_phys * phys_enc)311 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
312 struct dpu_encoder_phys *phys_enc)
313 {
314 struct dpu_crtc_state *dpu_cstate;
315
316 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
317 return BLEND_3D_NONE;
318
319 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
320
321 /* Use merge_3d unless DSC MERGE topology is used */
322 if (phys_enc->split_role == ENC_ROLE_SOLO &&
323 dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
324 !dpu_encoder_use_dsc_merge(phys_enc->parent))
325 return BLEND_3D_H_ROW_INT;
326
327 return BLEND_3D_NONE;
328 }
329
330 /**
331 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
332 * This helper function is used by physical encoder to get DSC blocks mask
333 * used for this encoder.
334 * @phys_enc: Pointer to physical encoder structure
335 */
336 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
337
338 /**
339 * dpu_encoder_helper_split_config - split display configuration helper function
340 * This helper function may be used by physical encoders to configure
341 * the split display related registers.
342 * @phys_enc: Pointer to physical encoder structure
343 * @interface: enum dpu_intf setting
344 */
345 void dpu_encoder_helper_split_config(
346 struct dpu_encoder_phys *phys_enc,
347 enum dpu_intf interface);
348
349 /**
350 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
351 * timed out, including reporting frame error event to crtc and debug dump
352 * @phys_enc: Pointer to physical encoder structure
353 * @intr_idx: Failing interrupt index
354 */
355 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
356 enum dpu_intr_idx intr_idx);
357
358 /**
359 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
360 * note: will call dpu_encoder_helper_wait_for_irq on timeout
361 * @phys_enc: Pointer to physical encoder structure
362 * @irq: IRQ index
363 * @func: IRQ callback to be called in case of timeout
364 * @wait_info: wait info struct
365 * @Return: 0 or -ERROR
366 */
367 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
368 int irq,
369 void (*func)(void *arg),
370 struct dpu_encoder_wait_info *wait_info);
371
372 /**
373 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
374 * @phys_enc: Pointer to physical encoder structure
375 */
376 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
377
378 /**
379 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
380 * @drm_enc: Pointer to drm encoder structure
381 * @phys_enc: Pointer to physical encoder
382 * Note: This is called from IRQ handler context.
383 */
384 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
385 struct dpu_encoder_phys *phy_enc);
386
387 /** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
388 * @drm_enc: Pointer to drm encoder structure
389 * @phys_enc: Pointer to physical encoder
390 * Note: This is called from IRQ handler context.
391 */
392 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
393 struct dpu_encoder_phys *phy_enc);
394
395 /** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame
396 * @drm_enc: Pointer to drm encoder structure
397 * @phys_enc: Pointer to physical encoder
398 * @event: Event to process
399 */
400 void dpu_encoder_frame_done_callback(
401 struct drm_encoder *drm_enc,
402 struct dpu_encoder_phys *ready_phys, u32 event);
403
404 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys,
405 struct dpu_enc_phys_init_params *p);
406
407 #endif /* __dpu_encoder_phys_H__ */
408